prev_cmp_oscillograph.map.qmsg

在EP1C6Q240上实现示波器的逻辑代码.Verilog编写!很好用.调试成功.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 06 15:37:47 2008 " "Info: Processing started: Thu Mar 06 15:37:47 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Oscillograph -c Oscillograph " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Oscillograph -c Oscillograph" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyDD/PLL.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyDD/PLL.v" { { "Info" "ISGN_ENTITY_NAME" "1 PLL " "Info: Found entity 1: PLL" {  } { { "MyDD/PLL.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/PLL.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyDD/Oscillograph.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyDD/Oscillograph.v" { { "Info" "ISGN_ENTITY_NAME" "1 Oscillograph " "Info: Found entity 1: Oscillograph" {  } { { "MyDD/Oscillograph.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Oscillograph " "Info: Elaborating entity \"Oscillograph\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "PLL PLL:PLL " "Info: Elaborating entity \"PLL\" for hierarchy \"PLL:PLL\"" {  } { { "MyDD/Oscillograph.v" "PLL" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 45 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 476 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll PLL:PLL\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"PLL:PLL\|altpll:altpll_component\"" {  } { { "MyDD/PLL.v" "altpll_component" { Text "E:/Study FPGA/Oscillograph/MyDD/PLL.v" 88 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "PLL:PLL\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"PLL:PLL\|altpll:altpll_component\"" {  } { { "MyDD/PLL.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/PLL.v" 88 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd 7 2 " "Info: Found 7 design units, including 2 entities, in source file c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_signaltap_pack " "Info: Found design unit 1: sld_signaltap_pack" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 62 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_signaltap_lib " "Info: Found design unit 2: sld_signaltap_lib" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 70 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 sld_signaltap_lib-body " "Info: Found design unit 3: sld_signaltap_lib-body" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 75 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 sld_signaltap-rtl " "Info: Found design unit 4: sld_signaltap-rtl" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 229 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 sld_signaltap_impl-rtl " "Info: Found design unit 5: sld_signaltap_impl-rtl" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 522 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_signaltap " "Info: Found entity 1: sld_signaltap" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 131 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_signaltap_impl " "Info: Found entity 2: sld_signaltap_impl" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_signaltap.vhd" 433 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file c:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 sld_ela_control-rtl " "Info: Found design unit 1: sld_ela_control-rtl" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" 129 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 sld_ela_basic_multi_level_trigger-rtl " "Info: Found design unit 2: sld_ela_basic_multi_level_trigger-rtl" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" 702 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 sld_ela_control " "Info: Found entity 1: sld_ela_control" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" 71 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 sld_ela_basic_multi_level_trigger " "Info: Found entity 2: sld_ela_basic_multi_level_trigger" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_ela_control.vhd" 669 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}