prev_cmp_oscillograph.qmsg

在EP1C6Q240上实现示波器的逻辑代码.Verilog编写!很好用.调试成功.

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s7 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s7\" with stuck data_in port to stuck value GND" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s8 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s8\" with stuck data_in port to stuck value GND" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s9 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s9\" with stuck data_in port to stuck value GND" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s10 data_in GND " "Warning (14130): Reduced register \"sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_ela_control:ela_control\|sld_ela_trigger_flow_mgr:\\builtin:ela_trigger_flow_mgr_entity\|state.s10\" with stuck data_in port to stuck value GND" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd" 52 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Info: Found the following redundant logic cells in design" {  } {  } 0 0 "Found the following redundant logic cells in design" 0 0 "" 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/72/quartus/libraries/megafunctions/sld_hub.vhd" 385 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "545 " "Info: Implemented 545 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "3 " "Info: Implemented 3 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "532 " "Info: Implemented 532 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0} { "Info" "ICUT_CUT_TM_RAMS" "2 " "Info: Implemented 2 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 9 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 9 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "182 " "Info: Allocated 182 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 06 14:25:18 2008 " "Info: Processing ended: Thu Mar 06 14:25:18 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Info: Elapsed time: 00:00:17" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 06 14:25:19 2008 " "Info: Processing started: Thu Mar 06 14:25:19 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off Oscillograph -c Oscillograph " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off Oscillograph -c Oscillograph" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "Oscillograph EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"Oscillograph\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0}
{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "PLL:PLL\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"PLL:PLL\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "PLL:PLL\|altpll:altpll_component\|_clk0 5 1 0 0 " "Info: Implementing clock multiplication of 5, clock division of 1, and phase shift of 0 degrees (0 ps) for PLL:PLL\|altpll:altpll_component\|_clk0 port" {  } {  } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0}  } { { "altpll.tdf" "" { Text "c:/altera/72/quartus/libraries/megafunctions/altpll.tdf" 895 3 0 } } { "MyDD/PLL.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/PLL.v" 88 0 0 } } { "MyDD/Oscillograph.v" "" { Text "E:/Study FPGA/Oscillograph/MyDD/Oscillograph.v" 45 0 0 } }  } 0 0 "Implementing parameter values for PLL \"%1!s!\"" 0 0 "" 0}