oscillograph.tan.summary

在EP1C6Q240上实现示波器的逻辑代码.Verilog编写!很好用.调试成功.

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.948 ns
From           : in_signal
To             : out_signal~reg0
From Clock     : --
To Clock       : inclk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 5.321 ns
From           : out_signal~reg0
To             : out_signal
From Clock     : inclk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 8.552 ns
From           : in_signal
To             : altera_auto_signaltap_0_in_signal_ae
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 3.983 ns
From           : altera_internal_jtag~TMSUTAP
To             : sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Setup: 'inclk'
Slack          : 1.471 ns
Required Time  : 40.00 MHz ( period = 25.000 ns )
Actual Time    : N/A
From           : trigger~reg0
To             : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1]
From Clock     : PLL:PLL|altpll:altpll_component|_clk0
To Clock       : inclk
Failed Paths   : 0

Type           : Clock Setup: 'PLL:PLL|altpll:altpll_component|_clk0'
Slack          : 3.672 ns
Required Time  : 200.00 MHz ( period = 5.000 ns )
Actual Time    : Restricted to 275.03 MHz ( period = 3.636 ns )
From           : trigger~reg0
To             : trigger~reg0
From Clock     : PLL:PLL|altpll:altpll_component|_clk0
To Clock       : PLL:PLL|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 60.75 MHz ( period = 16.462 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]
To             : sld_hub:sld_hub_inst|hub_tdo_reg
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'inclk'
Slack          : 0.822 ns
Required Time  : 40.00 MHz ( period = 25.000 ns )
Actual Time    : N/A
From           : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address[0]
To             : sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address[0]
From Clock     : inclk
To Clock       : inclk
Failed Paths   : 0

Type           : Clock Hold: 'PLL:PLL|altpll:altpll_component|_clk0'
Slack          : 1.276 ns
Required Time  : 200.00 MHz ( period = 5.000 ns )
Actual Time    : N/A
From           : trigger~reg0
To             : trigger~reg0
From Clock     : PLL:PLL|altpll:altpll_component|_clk0
To Clock       : PLL:PLL|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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