oscillograph.tan.rpt

在EP1C6Q240上实现示波器的逻辑代码.Verilog编写!很好用.调试成功.

; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; Off                ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                        ;
+---------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                       ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+---------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; PLL:PLL|altpll:altpll_component|_clk0 ;                    ; PLL output ; 200.0 MHz        ; 0.000 ns      ; 0.000 ns     ; inclk    ; 5                     ; 1                   ; -1.885 ns ;              ;
; inclk                                 ;                    ; User Pin   ; 40.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; altera_internal_jtag~TCKUTAP          ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+---------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'PLL:PLL|altpll:altpll_component|_clk0'                                                                                                                                                                                                       ;
+----------+-----------------------------------------------+--------------+--------------+---------------------------------------+---------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack    ; Actual fmax (period)                          ; From         ; To           ; From Clock                            ; To Clock                              ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+----------+-----------------------------------------------+--------------+--------------+---------------------------------------+---------------------------------------+-----------------------------+---------------------------+-------------------------+
; 3.672 ns ; Restricted to 275.03 MHz ( period = 3.64 ns ) ; trigger~reg0 ; trigger~reg0 ; PLL:PLL|altpll:altpll_component|_clk0 ; PLL:PLL|altpll:altpll_component|_clk0 ; 5.000 ns                    ; 4.739 ns                  ; 1.067 ns                ;
+----------+-----------------------------------------------+--------------+--------------+---------------------------------------+---------------------------------------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'inclk'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                               ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                    ; To                                                                                                                                                ; From Clock                            ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+----------+-----------------------------+---------------------------+-------------------------+
; 1.471 ns                                ; None                                                ; trigger~reg0                                                                                                                            ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1]                                                        ; PLL:PLL|altpll:altpll_component|_clk0 ; inclk    ; 1.885 ns                    ; 2.181 ns                  ; 0.710 ns                ;
; 1.475 ns                                ; None                                                ; trigger~reg0                                                                                                                            ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|trigger_in_reg                                                               ; PLL:PLL|altpll:altpll_component|_clk0 ; inclk    ; 1.885 ns                    ; 2.181 ns                  ; 0.706 ns                ;
; 1.478 ns                                ; None                                                ; trigger~reg0                                                                                                                            ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_data_in_reg[1]                                                           ; PLL:PLL|altpll:altpll_component|_clk0 ; inclk    ; 1.885 ns                    ; 2.181 ns                  ; 0.703 ns                ;
; 16.152 ns                               ; 113.02 MHz ( period = 8.848 ns )                    ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[7]              ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[0]                   ; inclk                                 ; inclk    ; 25.000 ns                   ; 24.739 ns                 ; 8.587 ns                ;
; 16.158 ns                               ; 113.10 MHz ( period = 8.842 ns )                    ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[7]              ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[2]                   ; inclk                                 ; inclk    ; 25.000 ns                   ; 24.739 ns                 ; 8.581 ns                ;
; 16.182 ns                               ; 113.40 MHz ( period = 8.818 ns )                    ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[2]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[0]                   ; inclk                                 ; inclk    ; 25.000 ns                   ; 24.739 ns                 ; 8.557 ns                ;
; 16.188 ns                               ; 113.48 MHz ( period = 8.812 ns )                    ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[2]  ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[2]                   ; inclk                                 ; inclk    ; 25.000 ns                   ; 24.739 ns                 ; 8.551 ns                ;
; 16.222 ns                               ; 113.92 MHz ( period = 8.778 ns )                    ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[8]              ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|next_address[0]                   ; inclk                                 ; inclk    ; 25.000 ns                   ; 24.739 ns                 ; 8.517 ns                ;