oscillograph.tan.rpt

在EP1C6Q240上实现示波器的逻辑代码.Verilog编写!很好用.调试成功.

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+------------------------------------------------------+----------+----------------------------------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------------------------------------+--------------+
; Type                                                 ; Slack    ; Required Time                    ; Actual Time                                    ; From                                                                                                                            ; To                                                                                                                              ; From Clock                            ; To Clock                              ; Failed Paths ;
+------------------------------------------------------+----------+----------------------------------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------------------------------------+--------------+
; Worst-case tsu                                       ; N/A      ; None                             ; 7.948 ns                                       ; in_signal                                                                                                                       ; out_signal~reg0                                                                                                                 ; --                                    ; inclk                                 ; 0            ;
; Worst-case tco                                       ; N/A      ; None                             ; 5.321 ns                                       ; out_signal~reg0                                                                                                                 ; out_signal                                                                                                                      ; inclk                                 ; --                                    ; 0            ;
; Worst-case tpd                                       ; N/A      ; None                             ; 8.552 ns                                       ; in_signal                                                                                                                       ; altera_auto_signaltap_0_in_signal_ae                                                                                            ; --                                    ; --                                    ; 0            ;
; Worst-case th                                        ; N/A      ; None                             ; 3.983 ns                                       ; altera_internal_jtag~TMSUTAP                                                                                                    ; sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]                                                         ; --                                    ; altera_internal_jtag~TCKUTAP          ; 0            ;
; Clock Setup: 'inclk'                                 ; 1.471 ns ; 40.00 MHz ( period = 25.000 ns ) ; N/A                                            ; trigger~reg0                                                                                                                    ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|acq_trigger_in_reg[1]                                      ; PLL:PLL|altpll:altpll_component|_clk0 ; inclk                                 ; 0            ;
; Clock Setup: 'PLL:PLL|altpll:altpll_component|_clk0' ; 3.672 ns ; 200.00 MHz ( period = 5.000 ns ) ; Restricted to 275.03 MHz ( period = 3.636 ns ) ; trigger~reg0                                                                                                                    ; trigger~reg0                                                                                                                    ; PLL:PLL|altpll:altpll_component|_clk0 ; PLL:PLL|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'          ; N/A      ; None                             ; 60.75 MHz ( period = 16.462 ns )               ; sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]                                                                                   ; sld_hub:sld_hub_inst|hub_tdo_reg                                                                                                ; altera_internal_jtag~TCKUTAP          ; altera_internal_jtag~TCKUTAP          ; 0            ;
; Clock Hold: 'inclk'                                  ; 0.822 ns ; 40.00 MHz ( period = 25.000 ns ) ; N/A                                            ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address[0] ; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|base_address[0] ; inclk                                 ; inclk                                 ; 0            ;
; Clock Hold: 'PLL:PLL|altpll:altpll_component|_clk0'  ; 1.276 ns ; 200.00 MHz ( period = 5.000 ns ) ; N/A                                            ; trigger~reg0                                                                                                                    ; trigger~reg0                                                                                                                    ; PLL:PLL|altpll:altpll_component|_clk0 ; PLL:PLL|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                         ;          ;                                  ;                                                ;                                                                                                                                 ;                                                                                                                                 ;                                       ;                                       ; 0            ;
+------------------------------------------------------+----------+----------------------------------+------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------------------------------------+--------------+


+---------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                      ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;