i2c_master_top.map.qmsg

I2C总线的逻辑代码.Verilog编写!很好用.调试成功.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 31 14:11:17 2007 " "Info: Processing started: Thu May 31 14:11:17 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off i2c_master_top -c i2c_master_top " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off i2c_master_top -c i2c_master_top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyDD/i2c_wreg.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyDD/i2c_wreg.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_wreg " "Info: Found entity 1: i2c_wreg" {  } { { "MyDD/i2c_wreg.v" "" { Text "C:/Documents and Settings/Administrator/桌面/I2C/MyDD/i2c_wreg.v" 45 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyDD/i2c.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyDD/i2c.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c " "Info: Found entity 1: i2c" {  } { { "MyDD/i2c.v" "" { Text "C:/Documents and Settings/Administrator/桌面/I2C/MyDD/i2c.v" 61 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyDD/i2c_clk.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyDD/i2c_clk.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_clk " "Info: Found entity 1: i2c_clk" {  } { { "MyDD/i2c_clk.v" "" { Text "C:/Documents and Settings/Administrator/桌面/I2C/MyDD/i2c_clk.v" 50 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyDD/i2c_rreg.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyDD/i2c_rreg.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_rreg " "Info: Found entity 1: i2c_rreg" {  } { { "MyDD/i2c_rreg.v" "" { Text "C:/Documents and Settings/Administrator/桌面/I2C/MyDD/i2c_rreg.v" 44 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyDD/i2c_st.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyDD/i2c_st.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_st " "Info: Found entity 1: i2c_st" {  } { { "MyDD/i2c_st.v" "" { Text "C:/Documents and Settings/Administrator/桌面/I2C/MyDD/i2c_st.v" 47 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_XZ_EXTEND_SIGNIFICANT" "i2c_tbuf.v(76) " "Warning (10273): Verilog HDL warning at i2c_tbuf.v(76): extended using \"x\" or \"z\"" {  } { { "MyDD/i2c_tbuf.v" "" { Text "C:/Documents and Settings/Administrator/桌面/I2C/MyDD/i2c_tbuf.v" 76 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "MyDD/i2c_tbuf.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file MyDD/i2c_tbuf.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c_tbuf " "Info: Found entity 1: i2c_tbuf" {  } { { "MyDD/i2c_tbuf.v" "" { Text "C:/Documents and Settings/Administrator/桌面/I2C/MyDD/i2c_tbuf.v" 44 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "ESGN_TOP_ENTITY_IS_MISSING" "i2c_master_top " "Error: Top-level design entity \"i2c_master_top\" is undefined" {  } {  } 0 0 "Top-level design entity \"%1!s!\" is undefined" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Thu May 31 14:11:18 2007 " "Error: Processing ended: Thu May 31 14:11:18 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Documents and Settings/Administrator/桌面/I2C/i2c_master_top.map.smsg " "Info: Generated suppressed messages file C:/Documents and Settings/Administrator/桌面/I2C/i2c_master_top.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}