i2c.smp_dump.txt

I2C总线的逻辑代码.Verilog编写!很好用.调试成功.

State Machine - |i2c|i2c_st:U4|i2c_state
Name i2c_state.dis_clk1 i2c_state.stop1 i2c_state.start2 i2c_state.start1 i2c_state.data i2c_state.w_add i2c_state.dev_add2 i2c_state.dev_add1 i2c_state.ack4 i2c_state.ack3 i2c_state.ack2 i2c_state.ack1 i2c_state.wait1 i2c_state.en_clk i2c_state.idle 
i2c_state.idle 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 
i2c_state.en_clk 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 
i2c_state.wait1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 
i2c_state.ack1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 
i2c_state.ack2 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 
i2c_state.ack3 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 
i2c_state.ack4 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 
i2c_state.dev_add1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 
i2c_state.dev_add2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 
i2c_state.w_add 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 
i2c_state.data 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 
i2c_state.start1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 
i2c_state.start2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 
i2c_state.stop1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 
i2c_state.dis_clk1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1