i2c.hif

I2C总线的逻辑代码.Verilog编写!很好用.调试成功.

Version 7.2 Build 151 09/26/2007 SJ Full Version
38
2265
OFF
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
i2c
# storage
db|i2c.(0).cnf
db|i2c.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
MyDD|i2c.v
cb815fab727f461bd7494e0a8bc7b9d
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
|
}
# lmf
c:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
i2c_wreg
# storage
db|i2c.(1).cnf
db|i2c.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
MyDD|i2c_wreg.v
8065e4beb3d35d1bafb478f7812ea92
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
w_add
00
PARAMETER_UNSIGNED_BIN
DEF
d_add
01
PARAMETER_UNSIGNED_BIN
DEF
s_add
10
PARAMETER_UNSIGNED_BIN
DEF
}
# hierarchies {
i2c_wreg:U1
}
# lmf
c:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
i2c_rreg
# storage
db|i2c.(2).cnf
db|i2c.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
MyDD|i2c_rreg.v
131b1e23afb927e6dad93b2e77548aca
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
w_add
00
PARAMETER_UNSIGNED_BIN
DEF
d_add
01
PARAMETER_UNSIGNED_BIN
DEF
s_add
10
PARAMETER_UNSIGNED_BIN
DEF
}
# hierarchies {
i2c_rreg:U2
}
# lmf
c:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
i2c_clk
# storage
db|i2c.(3).cnf
db|i2c.(3).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
MyDD|i2c_clk.v
592044114b30453e3f2e595f3259a7b
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
i2c_clk:U3
}
# lmf
c:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
i2c_st
# storage
db|i2c.(4).cnf
db|i2c.(4).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
MyDD|i2c_st.v
17346251bacddd681eb0eea34ac0179
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
idle
0000
PARAMETER_UNSIGNED_BIN
DEF
en_clk
0001
PARAMETER_UNSIGNED_BIN
DEF
start1
1100
PARAMETER_UNSIGNED_BIN
DEF
dev_add1
1000
PARAMETER_UNSIGNED_BIN
DEF
ack1
0100
PARAMETER_UNSIGNED_BIN
DEF
w_add
1010
PARAMETER_UNSIGNED_BIN
DEF
ack2
0101
PARAMETER_UNSIGNED_BIN
DEF
wait1
0011
PARAMETER_UNSIGNED_BIN
DEF
dis_clk1
1111
PARAMETER_UNSIGNED_BIN
DEF
start2
1101
PARAMETER_UNSIGNED_BIN
DEF
dev_add2
1001
PARAMETER_UNSIGNED_BIN
DEF
ack3
0110
PARAMETER_UNSIGNED_BIN
DEF
data
1011
PARAMETER_UNSIGNED_BIN
DEF
ack4
0111
PARAMETER_UNSIGNED_BIN
DEF
stop1
1110
PARAMETER_UNSIGNED_BIN
DEF
}
# hierarchies {
i2c_st:U4
}
# lmf
c:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
i2c_tbuf
# storage
db|i2c.(5).cnf
db|i2c.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
MyDD|i2c_tbuf.v
adc37e1d91272cacd9cb9cd05cc8f61f
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
i2c_tbuf:U5
}
# lmf
c:|altera|72|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# complete