minclock.vhd

VHDL的数字钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity minclock is
port (clk1khz, ena, clkadd: in std_logic;
      dtm, qtm: in std_logic_vector(3 downto 0);
      tf: out std_logic;
      dm, qm: out std_logic_vector(3 downto 0));
end minclock;
architecture one of minclock is
    signal dmf, qmf: std_logic_vector(3 downto 0);
begin
 process (clk1khz,ena,clkadd,dtm,qtm,dmf,qmf)
   begin
   if ena='0' then
    if rising_edge(clkadd) then
     if qmf="0101" and dmf="1001" then qmf<="0000"; dmf<="0000";               
     elsif dmf<"1001" then dmf<=dmf+1;
        elsif dmf="1001" then qmf<=qmf+1; dmf<="0000";
     end if;
    end if;
   elsif rising_edge(clk1khz) then
       if dtm=dmf and qtm=qmf then
       tf<='1';
       else tf<='0';
       end if;
   end if;
 dm<=dmf;
 qm<=qmf;
 end process;
end one;