yue.vhd

VHDL的数字钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity yue is
port (clk, ena: in std_logic;
          cout: out std_logic;
            mf: out std_logic_vector(1 downto 0);
        dy, qy: out std_logic_vector(3 downto 0));
end yue;
architecture one of yue is
signal dyt, qyt: std_logic_vector(3 downto 0);
signal mft:std_logic_vector(1 downto 0);
begin
process (clk, ena, dyt, qyt, mft)
   begin
   if ena='0' then
     qyt<="0000";
     dyt<="0001";
     mft<="10";
   elsif rising_edge(clk) then
       if (qyt="0001" and dyt="0010") then qyt<="0000"; dyt<="0001"; cout<='1';
       elsif dyt<"1001" then dyt<=dyt+1;  cout<='0';
       elsif dyt="1001" then qyt<=qyt+1; dyt<="0000"; cout<='0';
       end if;
       if((qyt="0000" and (dyt="0010" or dyt="0100" or dyt="0110" or dyt="0111" or dyt="1001")) or (qyt="0001" and (dyt="0001" or dyt="0010"))) then
       mft<="10";
       elsif((qyt="0000" and (dyt="0011" or dyt="0101" or dyt="1000")) or (qyt="0001" and dyt="0000")) then
          mft<="01";
          elsif (qyt="0000" and dyt="0001") then
             mft<="00";
       end if;
   end if;
   dy<=dyt;
   qy<=qyt;
   mf<=mft;
end process;
end one;