min.vhd

VHDL的数字钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity min is
port (clk, ena: in std_logic;
          cout: out std_logic;
        dm, qm: out std_logic_vector(3 downto 0));
end min;
architecture one of min is
    signal dmi, qmi: std_logic_vector (3 downto 0);
begin
process (clk, ena, dmi, qmi)
  begin
    if ena ='1' then 
      if clk'event and clk='1' then 
       if qmi="0101" and dmi="1001" then dmi<="0000"; qmi<="0000";
       elsif dmi<"1001" then dmi<=dmi+1;
          else dmi<="0000";
          if qmi<"0101" then qmi<=qmi+1;
          else qmi<="0000";
          end if;
       end if;
       if (qmi="0101" and dmi="1001") then cout <= '1';
       else cout<= '0';
       end if;
     end if;
    end if;
    dm <= dmi;
    qm <= qmi;
  end process;
end one;