sound.vhd

VHDL的数字钟

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sound is
  port(clk1khz,clk1hz,clk500hz: in std_logic;
       imq,imd,isq,isd:in std_logic_vector(3 downto 0);
       sound:out std_logic);     
  end sound;
architecture one of sound is
signal a,b,o1000,o500:std_logic;
begin
 process(clk1khz, clk1hz, clk500hz, imq, imd, isq, isd, o1000, o500, a, b)
  begin
   if rising_edge(clk1hz) then 
     if imq="0101" and imd="1001" and isq="0101" then
      if isd="0001" or isd="0011" or isd="0101" or isd="0111" then
      o500<='1';
      else o500<='0';
      end if;
     end if;
     if imq="0101" and imd="1001" and isq="0101" and isd="1001" then
      o1000<='1';
     else o1000<='0';
     end if;
   end if;
   a<=o1000 and clk1khz;
   b<=o500 and clk500hz;
   sound<=a or b;
 end process;
end one;