fir2.fnsim.qmsg

基于verilog的FIR滤波器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Web Edition " "Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jun 05 18:26:24 2007 " "Info: Processing started: Tue Jun 05 18:26:24 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off FIR2 -c FIR2 --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FIR2 -c FIR2 --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "add_tree.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file add_tree.v" { { "Info" "ISGN_ENTITY_NAME" "1 add_tree " "Info: Found entity 1: add_tree" {  } { { "add_tree.v" "" { Text "D:/altera/qdesigns60/My_design/FIR2/add_tree.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FIR2.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file FIR2.v" { { "Info" "ISGN_ENTITY_NAME" "1 FIR2 " "Info: Found entity 1: FIR2" {  } { { "FIR2.v" "" { Text "D:/altera/qdesigns60/My_design/FIR2/FIR2.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "FIR2 " "Info: Elaborating entity \"FIR2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_tree add_tree:r1 " "Info: Elaborating entity \"add_tree\" for hierarchy \"add_tree:r1\"" {  } { { "FIR2.v" "r1" { Text "D:/altera/qdesigns60/My_design/FIR2/FIR2.v" 35 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "#0 r4 9 16 " "Warning: Port \"#0\" on the entity instantiation of \"r4\" is connected to a signal of width 9. The formal width of the signal in the module is 16.  Extra bits will be left dangling without any fanout logic." {  } { { "FIR2.v" "r4" { Text "D:/altera/qdesigns60/My_design/FIR2/FIR2.v" 38 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT" "#1 r4 5 8 " "Warning: Port \"#1\" on the entity instantiation of \"r4\" is connected to a signal of width 5. The formal width of the signal in the module is 8.  Extra bits will be driven by GND." {  } { { "FIR2.v" "r4" { Text "D:/altera/qdesigns60/My_design/FIR2/FIR2.v" 38 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT" "#2 r4 4 8 " "Warning: Port \"#2\" on the entity instantiation of \"r4\" is connected to a signal of width 4. The formal width of the signal in the module is 8.  Extra bits will be driven by GND." {  } { { "FIR2.v" "r4" { Text "D:/altera/qdesigns60/My_design/FIR2/FIR2.v" 38 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "#0 r3 9 16 " "Warning: Port \"#0\" on the entity instantiation of \"r3\" is connected to a signal of width 9. The formal width of the signal in the module is 16.  Extra bits will be left dangling without any fanout logic." {  } { { "FIR2.v" "r3" { Text "D:/altera/qdesigns60/My_design/FIR2/FIR2.v" 37 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT" "#1 r3 5 8 " "Warning: Port \"#1\" on the entity instantiation of \"r3\" is connected to a signal of width 5. The formal width of the signal in the module is 8.  Extra bits will be driven by GND." {  } { { "FIR2.v" "r3" { Text "D:/altera/qdesigns60/My_design/FIR2/FIR2.v" 37 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT" "#2 r3 4 8 " "Warning: Port \"#2\" on the entity instantiation of \"r3\" is connected to a signal of width 4. The formal width of the signal in the module is 8.  Extra bits will be driven by GND." {  } { { "FIR2.v" "r3" { Text "D:/altera/qdesigns60/My_design/FIR2/FIR2.v" 37 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "#0 r2 9 16 " "Warning: Port \"#0\" on the entity instantiation of \"r2\" is connected to a signal of width 9. The formal width of the signal in the module is 16.  Extra bits will be left dangling without any fanout logic." {  } { { "FIR2.v" "r2" { Text "D:/altera/qdesigns60/My_design/FIR2/FIR2.v" 36 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT" "#1 r2 5 8 " "Warning: Port \"#1\" on the entity instantiation of \"r2\" is connected to a signal of width 5. The formal width of the signal in the module is 8.  Extra bits will be driven by GND." {  } { { "FIR2.v" "r2" { Text "D:/altera/qdesigns60/My_design/FIR2/FIR2.v" 36 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT" "#2 r2 4 8 " "Warning: Port \"#2\" on the entity instantiation of \"r2\" is connected to a signal of width 4. The formal width of the signal in the module is 8.  Extra bits will be driven by GND." {  } { { "FIR2.v" "r2" { Text "D:/altera/qdesigns60/My_design/FIR2/FIR2.v" 36 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_OUTPUT_PORT" "#0 r1 9 16 " "Warning: Port \"#0\" on the entity instantiation of \"r1\" is connected to a signal of width 9. The formal width of the signal in the module is 16.  Extra bits will be left dangling without any fanout logic." {  } { { "FIR2.v" "r1" { Text "D:/altera/qdesigns60/My_design/FIR2/FIR2.v" 35 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be left dangling without any fanout logic." 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT" "#1 r1 5 8 " "Warning: Port \"#1\" on the entity instantiation of \"r1\" is connected to a signal of width 5. The formal width of the signal in the module is 8.  Extra bits will be driven by GND." {  } { { "FIR2.v" "r1" { Text "D:/altera/qdesigns60/My_design/FIR2/FIR2.v" 35 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT" "#2 r1 4 8 " "Warning: Port \"#2\" on the entity instantiation of \"r1\" is connected to a signal of width 4. The formal width of the signal in the module is 8.  Extra bits will be driven by GND." {  } { { "FIR2.v" "r1" { Text "D:/altera/qdesigns60/My_design/FIR2/FIR2.v" 35 -1 0 } }  } 0 0 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  Extra bits will be driven by GND." 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add_tree:r4\|a_temp\[13\] data_in GND " "Warning: Reduced register \"add_tree:r4\|a_temp\[13\]\" with stuck data_in port to stuck value GND" {  } { { "add_tree.v" "" { Text "D:/altera/qdesigns60/My_design/FIR2/add_tree.v" 53 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add_tree:r4\|a_temp\[12\] data_in GND " "Warning: Reduced register \"add_tree:r4\|a_temp\[12\]\" with stuck data_in port to stuck value GND" {  } { { "add_tree.v" "" { Text "D:/altera/qdesigns60/My_design/FIR2/add_tree.v" 53 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add_tree:r4\|a_temp\[11\] data_in GND " "Warning: Reduced register \"add_tree:r4\|a_temp\[11\]\" with stuck data_in port to stuck value GND" {  } { { "add_tree.v" "" { Text "D:/altera/qdesigns60/My_design/FIR2/add_tree.v" 53 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add_tree:r4\|a_temp\[10\] data_in GND " "Warning: Reduced register \"add_tree:r4\|a_temp\[10\]\" with stuck data_in port to stuck value GND" {  } { { "add_tree.v" "" { Text "D:/altera/qdesigns60/My_design/FIR2/add_tree.v" 53 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add_tree:r4\|a_temp\[9\] data_in GND " "Warning: Reduced register \"add_tree:r4\|a_temp\[9\]\" with stuck data_in port to stuck value GND" {  } { { "add_tree.v" "" { Text "D:/altera/qdesigns60/My_design/FIR2/add_tree.v" 53 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add_tree:r4\|a_temp\[8\] data_in GND " "Warning: Reduced register \"add_tree:r4\|a_temp\[8\]\" with stuck data_in port to stuck value GND" {  } { { "add_tree.v" "" { Text "D:/altera/qdesigns60/My_design/FIR2/add_tree.v" 53 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add_tree:r4\|a_temp\[7\] data_in GND " "Warning: Reduced register \"add_tree:r4\|a_temp\[7\]\" with stuck data_in port to stuck value GND" {  } { { "add_tree.v" "" { Text "D:/altera/qdesigns60/My_design/FIR2/add_tree.v" 53 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add_tree:r4\|a_temp\[6\] data_in GND " "Warning: Reduced register \"add_tree:r4\|a_temp\[6\]\" with stuck data_in port to stuck value GND" {  } { { "add_tree.v" "" { Text "D:/altera/qdesigns60/My_design/FIR2/add_tree.v" 53 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add_tree:r4\|a_temp\[5\] data_in GND " "Warning: Reduced register \"add_tree:r4\|a_temp\[5\]\" with stuck data_in port to stuck value GND" {  } { { "add_tree.v" "" { Text "D:/altera/qdesigns60/My_design/FIR2/add_tree.v" 53 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add_tree:r4\|a_temp\[4\] data_in GND " "Warning: Reduced register \"add_tree:r4\|a_temp\[4\]\" with stuck data_in port to stuck value GND" {  } { { "add_tree.v" "" { Text "D:/altera/qdesigns60/My_design/FIR2/add_tree.v" 53 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add_tree:r4\|a_temp\[3\] data_in GND " "Warning: Reduced register \"add_tree:r4\|a_temp\[3\]\" with stuck data_in port to stuck value GND" {  } { { "add_tree.v" "" { Text "D:/altera/qdesigns60/My_design/FIR2/add_tree.v" 53 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add_tree:r4\|a_temp\[2\] data_in GND " "Warning: Reduced register \"add_tree:r4\|a_temp\[2\]\" with stuck data_in port to stuck value GND" {  } { { "add_tree.v" "" { Text "D:/altera/qdesigns60/My_design/FIR2/add_tree.v" 53 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add_tree:r4\|a_temp\[1\] data_in GND " "Warning: Reduced register \"add_tree:r4\|a_temp\[1\]\" with stuck data_in port to stuck value GND" {  } { { "add_tree.v" "" { Text "D:/altera/qdesigns60/My_design/FIR2/add_tree.v" 53 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add_tree:r4\|a_temp\[0\] data_in GND " "Warning: Reduced register \"add_tree:r4\|a_temp\[0\]\" with stuck data_in port to stuck value GND" {  } { { "add_tree.v" "" { Text "D:/altera/qdesigns60/My_design/FIR2/add_tree.v" 53 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add_tree:r4\|a_temp1\[13\] data_in GND " "Warning: Reduced register \"add_tree:r4\|a_temp1\[13\]\" with stuck data_in port to stuck value GND" {  } { { "add_tree.v" "" { Text "D:/altera/qdesigns60/My_design/FIR2/add_tree.v" 53 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "add_tree:r4\|a_temp1\[12\] data_in GND " "Warning: Reduced register \"add_tree:r4\|a_temp1\[12\]\" with stuck data_in port to stuck value GND" {  } { { "add_tree.v" "" { Text "D:/altera/qdesigns60/My_design/FIR2/add_tree.v" 53 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}