fir2.v

基于verilog的FIR滤波器

module FIR2(out,x,clk);
output[10:0] out;
input[3:0] x;
input clk;
reg[3:0] xfirst,xsecond,xthird,xfourth,xfifth,xsixth,xseventh,xeighth;
reg[4:0] s1,s2,s3,s4;
wire[8:0] yfirst,ysecond,ythird,yfourth;
reg[10:0] out;
reg[9:0] out1,out2;
//定义滤波器系数
parameter
h1=4'b0110,    h2=4'b0010,
h3=4'b0011,    h4=4'b0100;

always@(posedge clk)   
      begin                     //该begin-end语句块实现滤波器的延时处理,8级缓存
           xfirst   <=  x;
           xsecond  <=  xfirst;
           xthird   <=  xsecond;
           xfourth  <=  xthird;
           xfifth   <=  xfourth;
           xsixth   <=  xfifth;
           xseventh <=  xsixth;
           xeighth  <=  xseventh;
      end

always@(posedge clk)
      begin
           s1  = xfirst+xeighth;
           s2  = xsecond+xseventh;
           s3  = xthird+xsixth;
           s4  = xfourth+xfifth;
      end

add_tree   r1(yfirst,s1,h1,clk),   //乘法操作采用加法树实现
           r2(ysecond,s2,h2,clk),
           r3(ythird,s3,h3,clk),
           r4(yfourth,s4,h4,clk);

always@(posedge clk)
      begin
           out1   =  yfirst+ysecond;
           out2   =  ythird+yfourth;
           out    =  out1+out2;
      end
endmodule