fir1.v

基于verilog的FIR滤波器

module FIR1(out,x,clk);
output[10:0] out;
input[3:0] x;
input clk;
reg[3:0] xfirst,xsecond,xthird,xfourth,xfifth,xsixth,xseventh,xeighth;
wire[7:0] yfirst,ysecond,ythird,yfourth,yfifth,ysixth,yseventh,yeighth;
reg[10:0] out;
reg[8:0] out1,out2,out3,out4;
//定义滤波器系数
parameter
h1=4'b0110,    h2=4'b0010,
h3=4'b0011,    h4=4'b0100,
h5=4'b0100,    h6=4'b0011,
h7=4'b0010,    h8=4'b0110;

always@(posedge clk)   
      begin      //该begin-end语句块实现滤波器的延时处理,8级缓存
           xfirst   <=  x;
           xsecond  <=  xfirst;
           xthird   <=  xsecond;
           xfourth  <=  xthird;
           xfifth   <=  xfourth;
           xsixth   <=  xfifth;
           xseventh <=  xsixth;
           xeighth  <=  xseventh;
      end

add_tree   r1(yfirst,xfirst,h1,clk),   //乘法操作采用加法树实现
           r2(ysecond,xsecond,h2,clk),
           r3(ythird,xthird,h3,clk),
           r4(yfourth,xfourth,h4,clk),
           r5(yfifth,xfifth,h5,clk),
           r6(ysixth,xsixth,h6,clk),
           r7(yseventh,xseventh,h7,clk),
           r8(yeighth,xeighth,h8,clk);

always@(posedge clk)
      begin
           out1   =  yfirst+ysecond;
           out2   =  ythird+yfourth;
           out3   =  yfifth+ysixth;
           out4   =  yseventh+yeighth;
           out    =  out1+out2+out3+out4;
      end
endmodule