add_tree.v

基于verilog的FIR滤波器

module add_tree(out,a,b,clk);
output[15:0] out;
input[7:0] a,b;
input clk;
wire[15:0] out;
wire[15:0] out1,c1;
wire[13:0] out2;
wire[11:0] out3,c2;
wire[9:0] out4;

reg[14:0] a_temp;
reg[13:0] a_temp1;
reg[12:0] a_temp2;
reg[11:0] a_temp3;
reg[10:0] a_temp4;
reg[9:0] a_temp5;
reg[8:0] a_temp6;
reg[7:0] a_temp7;

assign out1=a_temp+a_temp1;
assign out2=a_temp2+a_temp3;
assign out3=a_temp4+a_temp5;
assign out4=a_temp6+a_temp7;
assign c1=out1+out2;
assign c2=out3+out4;
assign out=c1+c2;

function[7:0] and81;
input[7:0] operand;
input sel;
  begin
     and81 = (sel) ? (operand) : 8'h00;
  end
endfunction

always@(posedge clk)
   begin
        a_temp[14:7]=and81(a,b[7]);
        a_temp[6:0]=7'b0000000;
        a_temp1[13:6]=and81(a,b[6]);
        a_temp1[5:0]=6'b000000;
        a_temp2[12:5]=and81(a,b[5]);
        a_temp2[4:0]=5'b00000;
        a_temp3[11:4]=and81(a,b[4]);
        a_temp3[3:0]=4'b0000;
        a_temp4[10:3]=and81(a,b[3]);
        a_temp4[2:0]=3'b000;
        a_temp5[9:2]=and81(a,b[2]);
        a_temp5[1:0]=2'b00;
        a_temp6[8:1]=and81(a,b[1]);
        a_temp6[0]=0;
        a_temp7=and81(a,b[0]);
    end
endmodule