vhdl1.vhd.bak

用以实现信号的任意分频

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity pll is
port  ( clk:in std_logic;
		div:out std_logic);
end;

architecture one of pll is
	signal i:std_logic;
	signal count:integer:=0;
	signal clk_temp1:std_logic;
	signal clk_temp2:std_logic;
	signal clk_temp3:std_logic;
begin
process(clk)
begin
if clk'event and clk='1' then
	if count=0 then 
		count<=6;
		clk_temp3<='1';
		div<='1';
	else
		count<=count-1;
		clk_temp3<='0';
		div<='0';
	end if;
end if;
end process;
end;