decode.txt

verilog

module code_decode(rest,clk,en,start,Dout,Vin);
parameter size=7,
          with=4;
input rest,clk,en;
input[size-1:0]Vin;
reg[size-1:0]V_in;
output[size-1:0]Dout;
reg[size-1:0]Dout;

parameter  rdy=8'b10000000, 
          bit0=8'b01000000,
          bit1=8'b00100000,
          bit2=8'b00010000,
          bit3=8'b00001000,
          bit4=8'b00000100,
          bit5=8'b00000010,
          bit6=8'b00000001;
          
          
reg[7:0]p_s_sta; 
input start; 
reg Vx; 
reg en_out;      
always@(posedge clk or negedge rest) 
 if(!rest)
  begin
   p_s_sta<=rdy;
   Vx<=1'b0;
   en_out<=0;
  end   
else 
 if(start)
     case(p_s_sta)
         
       
       rdy:     begin
                 p_s_sta<=bit0;
                 Vx<=V_in[0];
                 en_out<=0;
                  end    
      bit0: begin
             p_s_sta<=bit1;
             Vx<=V_in[1];
             en_out<=0;
             end 
      bit1: begin
             p_s_sta<=bit2;
             Vx<=V_in[2];
             en_out<=0;
             end 
      bit2: begin
             p_s_sta<=bit3;
             Vx<=V_in[3];
             en_out<=0;
             end 
      bit3: begin
             p_s_sta<=bit4;
             Vx<=V_in[4];
             en_out<=0;
             end 
      bit4: begin
             p_s_sta<=bit5;
             Vx<=V_in[5];
             en_out<=0;
             end 
      bit5: begin
             p_s_sta<=bit6;
             Vx<=V_in[6];
             en_out<=0;
             end 
      bit6: begin
             p_s_sta<=rdy;
             Vx<=0;
             en_out<=1;
             end 
         
             
                                                 
     default: begin
               p_s_sta<=rdy;
               Vx<=0;
                en_out<=0;
              end       
      endcase 
  
always@(negedge clk or negedge rest) 
  if(!rest)
     V_in<=0;
  else
    if(en_out)
       V_in<=Vin;
  
  
  
         
integer i;
 reg Dx;              
reg[size-with-1:0]SR;
parameter tap=3'b101;
reg[size-with-1:0]buff;

always@(posedge clk or negedge rest )
   if(!rest)
     SR<=0;
   else 
      
        for(i=0;i<size-with-1;i=i+1) 
          begin
              SR[i]<=SR[i+1];
              SR[size-with-1]<=Dx; 
          end
 always@(SR)
      for(i=0;i<=size-with-1;i=i+1) 
        if(tap[i])buff[i]=SR[i];
        else buff[i]=0;       
          
reg Bx; 

always@(buff or Vx)
    begin
         Bx=^buff;          
         Dx=Bx ^ Vx;
     end
reg[size-1:0]D_out;
always@(negedge clk or negedge rest )
      if(!rest)
        D_out<=0;
      else  
        begin
         D_out<=D_out>>1;
         D_out[size-1]<=Dx;
        end
always@(negedge clk or negedge rest)
   if(!rest)
     Dout<=0;
   else
     if(en_out) 
         Dout<=D_out;    
endmodule