code_decode_tst.txt

verilog

`timescale 1ns/1ns
module code_decode_tst;
parameter size=4,
    with=3;    
reg clk,rest;
reg start;
reg[size-1:0]Din;
wire[size+with-1:0]Vout; 
wire [size+with-1:0]Dout;
wire en_out;
always #2 clk=~clk;
initial
begin
  rest=1;
  clk=0;
  #2 rest=0;
  #5 rest=1;
     Din=4'b0000;
  #2 start=1;
  #28 Din=4'b1000;
  #28 Din=4'b0100;
  #28 Din=4'b1100;
  
  #28 Din=4'b0010;
  #28 Din=4'b1010;
  #28 Din=4'b0110;
  #28 Din=4'b1110;
  
  #28 Din=4'b0001;
  #28 Din=4'b1001;
  #28 Din=4'b0101;
  #28 Din=4'b1101;
  
  #28 Din=4'b0011;
  #28 Din=4'b1011;
  #28 Din=4'b0111;
  #28 Din=4'b1111;
end
  
crc_3    crc_3_testbench(rest,clk,start,Din,Vout,en_out); 
code_decode   code_decode_tstbench(.rest(rest),.clk(clk),.en(en_out),.start(start),.Dout(Dout),.Vin(Vout));  
endmodule