seg7_1.map.qmsg

输入一个四位二进制数

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Full Version " "Info: Version 4.1 Build 181 06/29/2004 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 10 10:56:01 2006 " "Info: Processing started: Mon Apr 10 10:56:01 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --import_settings_files=on --export_settings_files=off seg7_1 -c seg7_1 " "Info: Command: quartus_map --import_settings_files=on --export_settings_files=off seg7_1 -c seg7_1" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "seg7_1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file seg7_1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 seg7_1-seg7_1_arch " "Info: Found design unit 1: seg7_1-seg7_1_arch" {  } { { "g:/study/experience/新建文件夹/seg7_1.vhd" "seg7_1-seg7_1_arch" "" { Text "g:/study/experience/新建文件夹/seg7_1.vhd" 9 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 seg7_1 " "Info: Found entity 1: seg7_1" {  } { { "g:/study/experience/新建文件夹/seg7_1.vhd" "seg7_1" "" { Text "g:/study/experience/新建文件夹/seg7_1.vhd" 3 -1 0 } }  } 0}  } {  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "seg7_1.vhd(30) " "Info: VHDL Case Statement information at seg7_1.vhd(30): OTHERS choice is never selected" {  } { { "g:/study/experience/新建文件夹/seg7_1.vhd" "" "" { Text "g:/study/experience/新建文件夹/seg7_1.vhd" 30 0 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "18 " "Info: Implemented 18 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "4 " "Info: Implemented 4 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "7 " "Info: Implemented 7 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_MCELLS" "7 " "Info: Implemented 7 macrocells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 10 10:56:04 2006 " "Info: Processing ended: Mon Apr 10 10:56:04 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}