4adder.map.qmsg

Quartus2实现的四位进制并行加法器 用VHDL语言实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 31 09:19:00 2008 " "Info: Processing started: Mon Mar 31 09:19:00 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off 4Adder -c 4Adder " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 4Adder -c 4Adder" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "4Adder.vhd 6 3 " "Info: Found 6 design units, including 3 entities, in source file 4Adder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Half_Adder-behave " "Info: Found design unit 1: Half_Adder-behave" {  } { { "4Adder.vhd" "" { Text "C:/Documents and Settings/new/桌面/4_Adder_Unique/4Adder.vhd" 10 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 Whole_Adder-Add " "Info: Found design unit 2: Whole_Adder-Add" {  } { { "4Adder.vhd" "" { Text "C:/Documents and Settings/new/桌面/4_Adder_Unique/4Adder.vhd" 26 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 Four_Adder-Four_Add " "Info: Found design unit 3: Four_Adder-Four_Add" {  } { { "4Adder.vhd" "" { Text "C:/Documents and Settings/new/桌面/4_Adder_Unique/4Adder.vhd" 56 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Half_Adder " "Info: Found entity 1: Half_Adder" {  } { { "4Adder.vhd" "" { Text "C:/Documents and Settings/new/桌面/4_Adder_Unique/4Adder.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 Whole_Adder " "Info: Found entity 2: Whole_Adder" {  } { { "4Adder.vhd" "" { Text "C:/Documents and Settings/new/桌面/4_Adder_Unique/4Adder.vhd" 20 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 Four_Adder " "Info: Found entity 3: Four_Adder" {  } { { "4Adder.vhd" "" { Text "C:/Documents and Settings/new/桌面/4_Adder_Unique/4Adder.vhd" 48 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Four_Adder " "Info: Elaborating entity \"Four_Adder\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Whole_Adder Whole_Adder:u1 " "Info: Elaborating entity \"Whole_Adder\" for hierarchy \"Whole_Adder:u1\"" {  } { { "4Adder.vhd" "u1" { Text "C:/Documents and Settings/new/桌面/4_Adder_Unique/4Adder.vhd" 86 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "Half_Adder Whole_Adder:u1\|Half_Adder:u1 " "Info: Elaborating entity \"Half_Adder\" for hierarchy \"Whole_Adder:u1\|Half_Adder:u1\"" {  } { { "4Adder.vhd" "u1" { Text "C:/Documents and Settings/new/桌面/4_Adder_Unique/4Adder.vhd" 35 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "25 " "Info: Implemented 25 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "9 " "Info: Implemented 9 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "5 " "Info: Implemented 5 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "11 " "Info: Implemented 11 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 0 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "137 " "Info: Allocated 137 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 31 09:19:03 2008 " "Info: Processing ended: Mon Mar 31 09:19:03 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}