4adder.tan.qmsg

Quartus2实现的四位进制并行加法器 用VHDL语言实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.1 Build 201 11/27/2006 SJ Full Version " "Info: Version 6.1 Build 201 11/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Mar 31 09:19:25 2008 " "Info: Processing started: Mon Mar 31 09:19:25 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off 4Adder -c 4Adder --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off 4Adder -c 4Adder --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "c0 cout_high 16.243 ns Longest " "Info: Longest tpd from source pin \"c0\" to destination pin \"cout_high\" is 16.243 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns c0 1 PIN PIN_169 2 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_169; Fanout = 2; PIN Node = 'c0'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "" { c0 } "NODE_NAME" } } { "4Adder.vhd" "" { Text "C:/Documents and Settings/new/桌面/4_Adder_Unique/4Adder.vhd" 51 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(7.861 ns) + CELL(0.590 ns) 9.920 ns Whole_Adder:u4\|Half_Adder:u2\|f~361 2 COMB LC_X2_Y20_N3 2 " "Info: 2: + IC(7.861 ns) + CELL(0.590 ns) = 9.920 ns; Loc. = LC_X2_Y20_N3; Fanout = 2; COMB Node = 'Whole_Adder:u4\|Half_Adder:u2\|f~361'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "8.451 ns" { c0 Whole_Adder:u4|Half_Adder:u2|f~361 } "NODE_NAME" } } { "4Adder.vhd" "" { Text "C:/Documents and Settings/new/桌面/4_Adder_Unique/4Adder.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.114 ns) 10.474 ns Whole_Adder:u4\|Half_Adder:u2\|f~362 3 COMB LC_X2_Y20_N8 2 " "Info: 3: + IC(0.440 ns) + CELL(0.114 ns) = 10.474 ns; Loc. = LC_X2_Y20_N8; Fanout = 2; COMB Node = 'Whole_Adder:u4\|Half_Adder:u2\|f~362'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.554 ns" { Whole_Adder:u4|Half_Adder:u2|f~361 Whole_Adder:u4|Half_Adder:u2|f~362 } "NODE_NAME" } } { "4Adder.vhd" "" { Text "C:/Documents and Settings/new/桌面/4_Adder_Unique/4Adder.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.411 ns) + CELL(0.442 ns) 11.327 ns Whole_Adder:u4\|Half_Adder:u2\|f~363 4 COMB LC_X2_Y20_N5 2 " "Info: 4: + IC(0.411 ns) + CELL(0.442 ns) = 11.327 ns; Loc. = LC_X2_Y20_N5; Fanout = 2; COMB Node = 'Whole_Adder:u4\|Half_Adder:u2\|f~363'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.853 ns" { Whole_Adder:u4|Half_Adder:u2|f~362 Whole_Adder:u4|Half_Adder:u2|f~363 } "NODE_NAME" } } { "4Adder.vhd" "" { Text "C:/Documents and Settings/new/桌面/4_Adder_Unique/4Adder.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.442 ns) + CELL(0.114 ns) 11.883 ns cout_high~112 5 COMB LC_X2_Y20_N4 1 " "Info: 5: + IC(0.442 ns) + CELL(0.114 ns) = 11.883 ns; Loc. = LC_X2_Y20_N4; Fanout = 1; COMB Node = 'cout_high~112'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "0.556 ns" { Whole_Adder:u4|Half_Adder:u2|f~363 cout_high~112 } "NODE_NAME" } } { "4Adder.vhd" "" { Text "C:/Documents and Settings/new/桌面/4_Adder_Unique/4Adder.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.236 ns) + CELL(2.124 ns) 16.243 ns cout_high 6 PIN PIN_17 0 " "Info: 6: + IC(2.236 ns) + CELL(2.124 ns) = 16.243 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'cout_high'" {  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "4.360 ns" { cout_high~112 cout_high } "NODE_NAME" } } { "4Adder.vhd" "" { Text "C:/Documents and Settings/new/桌面/4_Adder_Unique/4Adder.vhd" 53 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.853 ns ( 29.88 % ) " "Info: Total cell delay = 4.853 ns ( 29.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.390 ns ( 70.12 % ) " "Info: Total interconnect delay = 11.390 ns ( 70.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/61/quartus/bin/TimingClosureFloorplan.fld" "" "16.243 ns" { c0 Whole_Adder:u4|Half_Adder:u2|f~361 Whole_Adder:u4|Half_Adder:u2|f~362 Whole_Adder:u4|Half_Adder:u2|f~363 cout_high~112 cout_high } "NODE_NAME" } } { "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/61/quartus/bin/Technology_Viewer.qrui" "16.243 ns" { c0 c0~out0 Whole_Adder:u4|Half_Adder:u2|f~361 Whole_Adder:u4|Half_Adder:u2|f~362 Whole_Adder:u4|Half_Adder:u2|f~363 cout_high~112 cout_high } { 0.000ns 0.000ns 7.861ns 0.440ns 0.411ns 0.442ns 2.236ns } { 0.000ns 1.469ns 0.590ns 0.114ns 0.442ns 0.114ns 2.124ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 0 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "104 " "Info: Allocated 104 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Mar 31 09:19:26 2008 " "Info: Processing ended: Mon Mar 31 09:19:26 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}