4adder.hif

Quartus2实现的四位进制并行加法器 用VHDL语言实现

Version 6.1 Build 201 11/27/2006 SJ Full Version
35
1935
OFF
OFF
OFF
OFF
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
Four_Adder
# storage
db|4Adder.(0).cnf
db|4Adder.(0).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
4Adder.vhd
656a0dbe97d3d5ee38a6b30b9e5b06a
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
|
}
# end
# entity
Whole_Adder
# storage
db|4Adder.(1).cnf
db|4Adder.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
4Adder.vhd
656a0dbe97d3d5ee38a6b30b9e5b06a
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
Whole_Adder:u1
Whole_Adder:u2
Whole_Adder:u3
Whole_Adder:u4
}
# end
# entity
Half_Adder
# storage
db|4Adder.(2).cnf
db|4Adder.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
4Adder.vhd
656a0dbe97d3d5ee38a6b30b9e5b06a
4
# internal_option {
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
Whole_Adder:u1|Half_Adder:u1
Whole_Adder:u1|Half_Adder:u2
Whole_Adder:u2|Half_Adder:u1
Whole_Adder:u2|Half_Adder:u2
Whole_Adder:u3|Half_Adder:u1
Whole_Adder:u3|Half_Adder:u2
Whole_Adder:u4|Half_Adder:u1
Whole_Adder:u4|Half_Adder:u2
}
# end
# complete