4adder.fit.summary

Quartus2实现的四位进制并行加法器 用VHDL语言实现

Fitter Status : Successful - Mon Mar 31 09:19:13 2008
Quartus II Version : 6.1 Build 201 11/27/2006 SJ Full Version
Revision Name : 4Adder
Top-level Entity Name : Four_Adder
Family : Cyclone
Device : EP1C6Q240C8
Timing Models : Final
Total logic elements : 8 / 5,980 ( < 1 % )
Total pins : 14 / 185 ( 8 % )
Total virtual pins : 0
Total memory bits : 0 / 92,160 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )