fenpin1.vhd

VHDL分频器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;

entity fenpin1 is
  port(F_IN:in std_logic;
       F_OUT:out std_logic);
end fenpin1;

architecture a of fenpin1 is
signal FS_CTL:bit;
signal FOUT_9,FOUT_8,C_ENB:std_logic;
signal q:integer range 0 to 27;
signal F_9:integer range 0 to 8;
signal F_8:integer range 0 to 7;

begin

  p1:process(F_IN)
  begin
    if(F_IN'event and F_IN='1')then
      if C_ENB='1' then
        if q=27 then q<=0;
        else q<=q+1;
        end if;
      end if;
    end if;
  end process;

  p2:process(F_IN)
  begin
    if(q=1 or q=4 or q=7 or q=10 or q=13 or q=16
         or q=19 or q=22 or q=25 or q=27) then FS_CTL<='1';
    else FS_CTL<='0';
    end if;
  end process;

  p3:process(F_IN)
  begin
    if(F_IN'event and F_IN='1')then
      if(q=1 or q=4 or q=7 or q=10 or q=13 or q=16
         or q=19 or q=22 or q=25 or q=27) then
        if F_9=8 then 
          F_9<=0;
          C_ENB<='1';
        else 
          F_9<=F_9+1;
          C_ENB<='0';
        end if;
        if F_9<5 then FOUT_9<='0';
        else FOUT_9<='1';
        end if;
      else
        if F_8=7 then 
          F_8<=0;
          C_ENB<='1';
        else 
          F_8<=F_8+1;
          C_ENB<='0';
        end if;
        if F_8<4 then FOUT_8<='0';
        else FOUT_8<='1';
        end if;
      end if;
    end if;
  end process;

  p4:process(F_IN)
  begin
    case FS_CTL is
      when '0' =>F_OUT<=FOUT_8;
      when '1' =>F_OUT<=FOUT_9;
    end case;
  end process;

end;