fenpin.vhd

VHDL分频器

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;

entity fenpin is
  port(F_IN:in std_logic;
       F_OUT:out std_logic;
       F_OU:out std_logic);
end fenpin;

architecture a of fenpin is

component fenpin1
  port(F_IN:in std_logic;
       F_OUT:out std_logic);
end component;


begin
u1:fenpin1 port map(F_IN,F_OUT);

end;