send.vhd

FPGA的串口通信程序

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;

entity send is
port 
(
	  clk16x : in std_logic;
	  clk	 : in std_logic;
	  ctrl	 : in std_logic;
	  datain : in std_logic_vector(7 downto 0) ;
	  dout	 : out std_logic
);
end send ;

architecture rtl of send is

signal clk1x_enable : std_logic ;
signal tsr : std_logic_vector (7 downto 0) ;
signal tbr : std_logic_vector (7 downto 0) ;
signal clkdiv :  unsigned (3 downto 0) ;
signal no_bits_sent :  unsigned (3 downto 0) ;
signal clk1x : std_logic;

begin

process (clk)
begin
if clk'event and clk = '1' then
if ctrl = '1' then
		clk1x_enable <= '1' ;
	elsif std_logic_vector(no_bits_sent) = "1101" then
		clk1x_enable <= '0' ;					--使能信号，保证数据发送时的准确性
end if ;
end if ;
end process ;									--clk1x_enable与no_bits_send配合使用

process (clk16x,clk1x_enable)
begin
if clk16x'event and clk16x = '1' then
if std_logic_vector(clkdiv) = "1111" then
clkdiv <= "0000";
elsif clk1x_enable = '1' then
clkdiv <= clkdiv + "0001" ;
end if ;
end if ;
end process ;

clk1x <= clkdiv(3) ;

process (clk1x_enable)
begin
if clk1x_enable'event and clk1x_enable = '1' then
	tbr <= datain ;
end if ;
end process ;

process (clk1x,no_bits_sent,tbr)
begin
if clk1x'event and clk1x = '1' then
	if std_logic_vector(no_bits_sent) = "0001" then
		tsr <= tbr ;
	elsif std_logic_vector(no_bits_sent) = "0010" then
		dout <= '0';
	elsif std_logic_vector(no_bits_sent) >= "0011" and std_logic_vector(no_bits_sent) <= "1010" then
		tsr <= tsr(6 downto 0) & '0';
		dout <= tsr(7);
	elsif std_logic_vector(no_bits_sent) = "1011" then
		dout <= '1';
	end if ;
end if ;
end process ;

process (clk1x, clk1x_enable)
begin
if clk1x'event and clk1x = '1' then
	if clk1x_enable = '0' then
		no_bits_sent <= "0000" ;
	else
		no_bits_sent <= no_bits_sent + "0001" ;
end if ;
end if ;
end process ;

end ;