image.tan.qmsg

FPGA的串口通信程序

{ "Warning" "WTAN_FULL_MINIMUM_REQUIREMENTS_NOT_MET" "clk 32 " "Warning: Can't achieve minimum setup and hold requirement clk along 32 path(s). See Report window for details." {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "rs232_r:U1\|rcv:u2\|clk1x_enable rxd clk 4.271 ns register " "Info: tsu for register \"rs232_r:U1\|rcv:u2\|clk1x_enable\" (data pin = \"rxd\", clock pin = \"clk\") is 4.271 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.635 ns + Longest pin register " "Info: + Longest pin to register delay is 11.635 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rxd 1 PIN PIN_7 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_7; Fanout = 1; PIN Node = 'rxd'" {  } { { "D:/study/毕