image.tan.qmsg

FPGA的串口通信程序

{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'clk' 9 " "Warning: Can't achieve timing requirement Clock Setup: 'clk' along 9 path(s). See Report window for details." {  } {  } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "pll:U3\|altpll:altpll_component\|_clk0 register image1:U2\|level3in\[6\] register image1:U2\|shinningblock:U2\|out2_r_e\[6\] 862 ps " "Info: Minimum slack time is 862 ps for clock \"pll:U3\|altpll:altpll_component\|_clk0\" between source register \"image1:U2\|level3in\[6\]\" and destination register \"image1:U2\|shinningblock:U2\|out2_r_e\[6\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.653 ns + Shortest register register " "Info: + Shortest register to register delay is 0.653 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns image1:U2\|level3in\[6\] 1 REG LC_X26_Y13_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y13_N4; Fanout = 1; REG Node = 'image1:U2\|level3in\[6\]'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "" { image1:U2|level3in[6] } "NODE_NAME" } "" } } { "image1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image1.vhd" 76 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.538 ns) + CELL(0.115 ns) 0.653 ns image1:U2\|shinningblock:U2\|out2_r_e\[6\] 2 REG LC_X26_Y13_N2 1 " "Info: 2: + IC(0.538 ns) + CELL(0.115 ns) = 0.653 ns; Loc. = LC_X26_Y13_N2; Fanout = 1; REG Node = 'image1:U2\|shinningblock:U2\|out2_r_e\[6\]'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "0.653 ns" { image1:U2|level3in[6] image1:U2|shinningblock:U2|out2_r_e[6] } "NODE_NAME" } "" } } { "shinningblock.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/shinningblock.vhd" 55 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.115 ns 17.61 % " "Info: Total cell delay = 0.115 ns ( 17.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.538 ns 82.39 % " "Info: Total interconnect delay = 0.538 ns ( 82.39 % )" {  } {  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "0.653 ns" { image1:U2|level3in[6] image1:U2|shinningblock:U2|out2_r_e[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.653 ns" { image1:U2|level3in[6] image1:U2|shinningblock:U2|out2_r_e[6] } { 0.0ns 0.538ns } { 0.0ns 0.115ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.885 ns " "Info: + Latch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll:U3\|altpll:altpll_component\|_clk0 18.518 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"pll:U3\|altpll:altpll_component\|_clk0\" is 18.518 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.885 ns " "Info: - Launch edge is -1.885 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll:U3\|altpll:altpll_component\|_clk0 18.518 ns -1.885 ns  50 " "Info: Clock period of Source clock \"pll:U3\|altpll:altpll_component\|_clk0\" is 18.518 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:U3\|altpll:altpll_component\|_clk0 destination 2.405 ns + Longest register " "Info: + Longest clock path from clock \"pll:U3\|altpll:altpll_component\|_clk0\" to destination register is 2.405 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:U3\|altpll:altpll_component\|_clk0 1 CLK PLL_1 241 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 241; CLK Node = 'pll:U3\|altpll:altpll_component\|_clk0'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "" { pll:U3|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.694 ns) + CELL(0.711 ns) 2.405 ns image1:U2\|shinningblock:U2\|out2_r_e\[6\] 2 REG LC_X26_Y13_N2 1 " "Info: 2: + IC(1.694 ns) + CELL(0.711 ns) = 2.405 ns; Loc. = LC_X26_Y13_N2; Fanout = 1; REG Node = 'image1:U2\|shinningblock:U2\|out2_r_e\[6\]'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|shinningblock:U2|out2_r_e[6] } "NODE_NAME" } "" } } { "shinningblock.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/shinningblock.vhd" 55 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 29.56 % " "Info: Total cell delay = 0.711 ns ( 29.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.694 ns 70.44 % " "Info: Total interconnect delay = 1.694 ns ( 70.44 % )" {  } {  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|shinningblock:U2|out2_r_e[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|shinningblock:U2|out2_r_e[6] } { 0.0ns 1.694ns } { 0.0ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:U3\|altpll:altpll_component\|_clk0 source 2.405 ns - Shortest register " "Info: - Shortest clock path from clock \"pll:U3\|altpll:altpll_component\|_clk0\" to source register is 2.405 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:U3\|altpll:altpll_component\|_clk0 1 CLK PLL_1 241 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 241; CLK Node = 'pll:U3\|altpll:altpll_component\|_clk0'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "" { pll:U3|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.694 ns) + CELL(0.711 ns) 2.405 ns image1:U2\|level3in\[6\] 2 REG LC_X26_Y13_N4 1 " "Info: 2: + IC(1.694 ns) + CELL(0.711 ns) = 2.405 ns; Loc. = LC_X26_Y13_N4; Fanout = 1; REG Node = 'image1:U2\|level3in\[6\]'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|level3in[6] } "NODE_NAME" } "" } } { "image1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image1.vhd" 76 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 29.56 % " "Info: Total cell delay = 0.711 ns ( 29.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.694 ns 70.44 % " "Info: Total interconnect delay = 1.694 ns ( 70.44 % )" {  } {  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|level3in[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|level3in[6] } { 0.0ns 1.694ns } { 0.0ns 0.711ns } } }  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|shinningblock:U2|out2_r_e[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|shinningblock:U2|out2_r_e[6] } { 0.0ns 1.694ns } { 0.0ns 0.711ns } } } { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|level3in[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|level3in[6] } { 0.0ns 1.694ns } { 0.0ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "image1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image1.vhd" 76 -1 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "shinningblock.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/shinningblock.vhd" 55 -1 0 } }  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|shinningblock:U2|out2_r_e[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|shinningblock:U2|out2_r_e[6] } { 0.0ns 1.694ns } { 0.0ns 0.711ns } } } { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|level3in[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|level3in[6] } { 0.0ns 1.694ns } { 0.0ns 0.711ns } } }  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "0.653 ns" { image1:U2|level3in[6] image1:U2|shinningblock:U2|out2_r_e[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "0.653 ns" { image1:U2|level3in[6] image1:U2|shinningblock:U2|out2_r_e[6] } { 0.0ns 0.538ns } { 0.0ns 0.115ns } } } { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|shinningblock:U2|out2_r_e[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|shinningblock:U2|out2_r_e[6] } { 0.0ns 1.694ns } { 0.0ns 0.711ns } } } { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|level3in[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|level3in[6] } { 0.0ns 1.694ns } { 0.0ns 0.711ns } } }  } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk register rs232_t:u5\|send:u2\|clk1x_enable register rs232_t:u5\|send:u2\|no_bits_sent\[0\] -7.956 ns " "Info: Minimum slack time is -7.956 ns for clock \"clk\" between source register \"rs232_t:u5\|send:u2\|clk1x_enable\" and destination register \"rs232_t:u5\|send:u2\|no_bits_sent\[0\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.088 ns + Shortest register register " "Info: + Shortest register to register delay is 1.088 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rs232_t:u5\|send:u2\|clk1x_enable 1 REG LC_X8_Y10_N2 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N2; Fanout = 16; REG Node = 'rs232_t:u5\|send:u2\|clk1x_enable'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "" { rs232_t:u5|send:u2|clk1x_enable } "NODE_NAME" } "" } } { "send.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/send.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.610 ns) + CELL(0.478 ns) 1.088 ns rs232_t:u5\|send:u2\|no_bits_sent\[0\] 2 REG LC_X8_Y10_N7 9 " "Info: 2: + IC(0.610 ns) + CELL(0.478 ns) = 1.088 ns; Loc. = LC_X8_Y10_N7; Fanout = 9; REG Node = 'rs232_t:u5\|send:u2\|no_bits_sent\[0\]'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "1.088 ns" { rs232_t:u5|send:u2|clk1x_enable rs232_t:u5|send:u2|no_bits_sent[0] } "NODE_NAME" } "" } } { "send.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/send.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.478 ns 43.93 % " "Info: Total cell delay = 0.478 ns ( 43.93 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.610 ns 56.07 % " "Info: Total interconnect delay = 0.610 ns ( 56.07 % )" {  } {  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "1.088 ns" { rs232_t:u5|send:u2|clk1x_enable rs232_t:u5|send:u2|no_bits_sent[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.088 ns" { rs232_t:u5|send:u2|clk1x_enable rs232_t:u5|send:u2|no_bits_sent[0] } { 0.0ns 0.61ns } { 0.0ns 0.478ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "9.044 ns - Smallest register register " "Info: - Smallest register to register requirement is 9.044 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 25.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 25.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 25.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk\" is 25.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "9.253 ns + Smallest " "Info: + Smallest clock skew is 9.253 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.178 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 12.178 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 236 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 236; CLK Node = 'clk'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "" { clk } "NODE_NAME" } "" } } { "image.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns rs232_t:u5\|pll1:u1\|c0 2 REG LC_X27_Y10_N2 4 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N2; Fanout = 4; REG Node = 'rs232_t:u5\|pll1:u1\|c0'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "1.697 ns" { clk rs232_t:u5|pll1:u1|c0 } "NODE_NAME" } "" } } { "pll1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/pll1.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.506 ns) + CELL(0.935 ns) 7.607 ns rs232_t:u5\|send:u2\|clkdiv\[3\] 3 REG LC_X9_Y10_N8 15 " "Info: 3: + IC(3.506 ns) + CELL(0.935 ns) = 7.607 ns; Loc. = LC_X9_Y10_N8; Fanout = 15; REG Node = 'rs232_t:u5\|send:u2\|clkdiv\[3\]'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "4.441 ns" { rs232_t:u5|pll1:u1|c0 rs232_t:u5|send:u2|clkdiv[3] } "NODE_NAME" } "" } } { "send.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/send.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.860 ns) + CELL(0.711 ns) 12.178 ns rs232_t:u5\|send:u2\|no_bits_sent\[0\] 4 REG LC_X8_Y10_N7 9 " "Info: 4: + IC(3.860 ns) + CELL(0.711 ns) = 12.178 ns; Loc. = LC_X8_Y10_N7; Fanout = 9; REG Node = 'rs232_t:u5\|send:u2\|no_bits_sent\[0\]'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "4.571 ns" { rs232_t:u5|send:u2|clkdiv[3] rs232_t:u5|send:u2|no_bits_sent[0] } "NODE_NAME" } "" } } { "send.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/send.vhd" 22 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns 33.26 % " "Info: Total cell delay = 4.050 ns ( 33.26 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.128 ns 66.74 % " "Info: Total interconnect delay = 8.128 ns ( 66.74 % )" {  } {  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "12.178 ns" { clk rs232_t:u5|pll1:u1|c0 rs232_t:u5|send:u2|clkdiv[3] rs232_t:u5|send:u2|no_bits_sent[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.178 ns" { clk clk~out0 rs232_t:u5|pll1:u1|c0 rs232_t:u5|send:u2|clkdiv[3] rs232_t:u5|send:u2|no_bits_sent[0] } { 0.0ns 0.0ns 0.762ns 3.506ns 3.86ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.925 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.925 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 236 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 236; CLK Node = 'clk'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "" { clk } "NODE_NAME" } "" } } { "image.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.711 ns) 2.925 ns rs232_t:u5\|send:u2\|clk1x_enable 2 REG LC_X8_Y10_N2 16 " "Info: 2: + IC(0.745 ns) + CELL(0.711 ns) = 2.925 ns; Loc. = LC_X8_Y10_N2; Fanout = 16; REG Node = 'rs232_t:u5\|send:u2\|clk1x_enable'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "1.456 ns" { clk rs232_t:u5|send:u2|clk1x_enable } "NODE_NAME" } "" } } { "send.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/send.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 74.53 % " "Info: Total cell delay = 2.180 ns ( 74.53 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.745 ns 25.47 % " "Info: Total interconnect delay = 0.745 ns ( 25.47 % )" {  } {  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.925 ns" { clk rs232_t:u5|send:u2|clk1x_enable } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 rs232_t:u5|send:u2|clk1x_enable } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } }  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "12.178 ns" { clk rs232_t:u5|pll1:u1|c0 rs232_t:u5|send:u2|clkdiv[3] rs232_t:u5|send:u2|no_bits_sent[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.178 ns" { clk clk~out0 rs232_t:u5|pll1:u1|c0 rs232_t:u5|send:u2|clkdiv[3] rs232_t:u5|send:u2|no_bits_sent[0] } { 0.0ns 0.0ns 0.762ns 3.506ns 3.86ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.925 ns" { clk rs232_t:u5|send:u2|clk1x_enable } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 rs232_t:u5|send:u2|clk1x_enable } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "send.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/send.vhd" 18 -1 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "send.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/send.vhd" 22 -1 0 } }  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "12.178 ns" { clk rs232_t:u5|pll1:u1|c0 rs232_t:u5|send:u2|clkdiv[3] rs232_t:u5|send:u2|no_bits_sent[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.178 ns" { clk clk~out0 rs232_t:u5|pll1:u1|c0 rs232_t:u5|send:u2|clkdiv[3] rs232_t:u5|send:u2|no_bits_sent[0] } { 0.0ns 0.0ns 0.762ns 3.506ns 3.86ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.925 ns" { clk rs232_t:u5|send:u2|clk1x_enable } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 rs232_t:u5|send:u2|clk1x_enable } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } }  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "1.088 ns" { rs232_t:u5|send:u2|clk1x_enable rs232_t:u5|send:u2|no_bits_sent[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.088 ns" { rs232_t:u5|send:u2|clk1x_enable rs232_t:u5|send:u2|no_bits_sent[0] } { 0.0ns 0.61ns } { 0.0ns 0.478ns } } } { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "12.178 ns" { clk rs232_t:u5|pll1:u1|c0 rs232_t:u5|send:u2|clkdiv[3] rs232_t:u5|send:u2|no_bits_sent[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "12.178 ns" { clk clk~out0 rs232_t:u5|pll1:u1|c0 rs232_t:u5|send:u2|clkdiv[3] rs232_t:u5|send:u2|no_bits_sent[0] } { 0.0ns 0.0ns 0.762ns 3.506ns 3.86ns } { 0.0ns 1.469ns 0.935ns 0.935ns 0.711ns } } } { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.925 ns" { clk rs232_t:u5|send:u2|clk1x_enable } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.925 ns" { clk clk~out0 rs232_t:u5|send:u2|clk1x_enable } { 0.0ns 0.0ns 0.745ns } { 0.0ns 1.469ns 0.711ns } } }  } 0}