📄 image.tan.qmsg

📁 FPGA的串口通信程序
💻 QMSG
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{ "Info" "ITDB_FULL_SLACK_RESULT" "pll:U3\|altpll:altpll_component\|_clk0 register rs232_r:U1\|rcv:u2\|rgb_sel\[2\] register image1:U2\|out_g_e\[0\] -6.783 ns " "Info: Slack time is -6.783 ns for clock \"pll:U3\|altpll:altpll_component\|_clk0\" between source register \"rs232_r:U1\|rcv:u2\|rgb_sel\[2\]\" and destination register \"image1:U2\|out_g_e\[0\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-4.388 ns + Largest register register " "Info: + Largest register to register requirement is -4.388 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "0.890 ns + " "Info: + Setup relationship between source and destination is 0.890 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.890 ns " "Info: + Latch edge is 0.890 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll:U3\|altpll:altpll_component\|_clk0 18.518 ns -1.885 ns  50 " "Info: Clock period of Destination clock \"pll:U3\|altpll:altpll_component\|_clk0\" is 18.518 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk 25.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk\" is 25.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-5.017 ns + Largest " "Info: + Largest clock skew is -5.017 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:U3\|altpll:altpll_component\|_clk0 destination 2.405 ns + Shortest register " "Info: + Shortest clock path from clock \"pll:U3\|altpll:altpll_component\|_clk0\" to destination register is 2.405 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:U3\|altpll:altpll_component\|_clk0 1 CLK PLL_1 241 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 241; CLK Node = 'pll:U3\|altpll:altpll_component\|_clk0'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "" { pll:U3|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.694 ns) + CELL(0.711 ns) 2.405 ns image1:U2\|out_g_e\[0\] 2 REG LC_X28_Y15_N1 2 " "Info: 2: + IC(1.694 ns) + CELL(0.711 ns) = 2.405 ns; Loc. = LC_X28_Y15_N1; Fanout = 2; REG Node = 'image1:U2\|out_g_e\[0\]'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|out_g_e[0] } "NODE_NAME" } "" } } { "image1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image1.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns 29.56 % " "Info: Total cell delay = 0.711 ns ( 29.56 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.694 ns 70.44 % " "Info: Total interconnect delay = 1.694 ns ( 70.44 % )" {  } {  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|out_g_e[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|out_g_e[0] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.422 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 7.422 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 236 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 236; CLK Node = 'clk'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "" { clk } "NODE_NAME" } "" } } { "image.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.762 ns) + CELL(0.935 ns) 3.166 ns rs232_r:U1\|pll1:u1\|c0 2 REG LC_X27_Y10_N0 92 " "Info: 2: + IC(0.762 ns) + CELL(0.935 ns) = 3.166 ns; Loc. = LC_X27_Y10_N0; Fanout = 92; REG Node = 'rs232_r:U1\|pll1:u1\|c0'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "1.697 ns" { clk rs232_r:U1|pll1:u1|c0 } "NODE_NAME" } "" } } { "pll1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/pll1.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.545 ns) + CELL(0.711 ns) 7.422 ns rs232_r:U1\|rcv:u2\|rgb_sel\[2\] 3 REG LC_X29_Y15_N2 1 " "Info: 3: + IC(3.545 ns) + CELL(0.711 ns) = 7.422 ns; Loc. = LC_X29_Y15_N2; Fanout = 1; REG Node = 'rs232_r:U1\|rcv:u2\|rgb_sel\[2\]'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "4.256 ns" { rs232_r:U1|pll1:u1|c0 rs232_r:U1|rcv:u2|rgb_sel[2] } "NODE_NAME" } "" } } { "rcv.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/rcv.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 41.97 % " "Info: Total cell delay = 3.115 ns ( 41.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.307 ns 58.03 % " "Info: Total interconnect delay = 4.307 ns ( 58.03 % )" {  } {  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "7.422 ns" { clk rs232_r:U1|pll1:u1|c0 rs232_r:U1|rcv:u2|rgb_sel[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.422 ns" { clk clk~out0 rs232_r:U1|pll1:u1|c0 rs232_r:U1|rcv:u2|rgb_sel[2] } { 0.000ns 0.000ns 0.762ns 3.545ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|out_g_e[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|out_g_e[0] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } } { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "7.422 ns" { clk rs232_r:U1|pll1:u1|c0 rs232_r:U1|rcv:u2|rgb_sel[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.422 ns" { clk clk~out0 rs232_r:U1|pll1:u1|c0 rs232_r:U1|rcv:u2|rgb_sel[2] } { 0.000ns 0.000ns 0.762ns 3.545ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "rcv.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/rcv.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "image1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image1.vhd" 28 -1 0 } }  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|out_g_e[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|out_g_e[0] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } } { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "7.422 ns" { clk rs232_r:U1|pll1:u1|c0 rs232_r:U1|rcv:u2|rgb_sel[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.422 ns" { clk clk~out0 rs232_r:U1|pll1:u1|c0 rs232_r:U1|rcv:u2|rgb_sel[2] } { 0.000ns 0.000ns 0.762ns 3.545ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.395 ns - Longest register register " "Info: - Longest register to register delay is 2.395 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns rs232_r:U1\|rcv:u2\|rgb_sel\[2\] 1 REG LC_X29_Y15_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y15_N2; Fanout = 1; REG Node = 'rs232_r:U1\|rcv:u2\|rgb_sel\[2\]'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "" { rs232_r:U1|rcv:u2|rgb_sel[2] } "NODE_NAME" } "" } } { "rcv.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/rcv.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.552 ns) + CELL(0.590 ns) 1.142 ns rs232_r:U1\|rcv:u2\|rgb_sel\[2\]~156 2 COMB LC_X29_Y15_N9 24 " "Info: 2: + IC(0.552 ns) + CELL(0.590 ns) = 1.142 ns; Loc. = LC_X29_Y15_N9; Fanout = 24; COMB Node = 'rs232_r:U1\|rcv:u2\|rgb_sel\[2\]~156'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "1.142 ns" { rs232_r:U1|rcv:u2|rgb_sel[2] rs232_r:U1|rcv:u2|rgb_sel[2]~156 } "NODE_NAME" } "" } } { "rcv.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/rcv.vhd" 12 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.944 ns) + CELL(0.309 ns) 2.395 ns image1:U2\|out_g_e\[0\] 3 REG LC_X28_Y15_N1 2 " "Info: 3: + IC(0.944 ns) + CELL(0.309 ns) = 2.395 ns; Loc. = LC_X28_Y15_N1; Fanout = 2; REG Node = 'image1:U2\|out_g_e\[0\]'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "1.253 ns" { rs232_r:U1|rcv:u2|rgb_sel[2]~156 image1:U2|out_g_e[0] } "NODE_NAME" } "" } } { "image1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image1.vhd" 28 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.899 ns 37.54 % " "Info: Total cell delay = 0.899 ns ( 37.54 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.496 ns 62.46 % " "Info: Total interconnect delay = 1.496 ns ( 62.46 % )" {  } {  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.395 ns" { rs232_r:U1|rcv:u2|rgb_sel[2] rs232_r:U1|rcv:u2|rgb_sel[2]~156 image1:U2|out_g_e[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.395 ns" { rs232_r:U1|rcv:u2|rgb_sel[2] rs232_r:U1|rcv:u2|rgb_sel[2]~156 image1:U2|out_g_e[0] } { 0.000ns 0.552ns 0.944ns } { 0.000ns 0.590ns 0.309ns } } }  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|out_g_e[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.405 ns" { pll:U3|altpll:altpll_component|_clk0 image1:U2|out_g_e[0] } { 0.000ns 1.694ns } { 0.000ns 0.711ns } } } { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "7.422 ns" { clk rs232_r:U1|pll1:u1|c0 rs232_r:U1|rcv:u2|rgb_sel[2] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.422 ns" { clk clk~out0 rs232_r:U1|pll1:u1|c0 rs232_r:U1|rcv:u2|rgb_sel[2] } { 0.000ns 0.000ns 0.762ns 3.545ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.395 ns" { rs232_r:U1|rcv:u2|rgb_sel[2] rs232_r:U1|rcv:u2|rgb_sel[2]~156 image1:U2|out_g_e[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.395 ns" { rs232_r:U1|rcv:u2|rgb_sel[2] rs232_r:U1|rcv:u2|rgb_sel[2]~156 image1:U2|out_g_e[0] } { 0.000ns 0.552ns 0.944ns } { 0.000ns 0.590ns 0.309ns } } }  } 0}
{ "Warning" "WTAN_FULL_REQUIREMENTS_NOT_MET" "Clock Setup: 'pll:U3\|altpll:altpll_component\|_clk0' 283 " "Warning: Can't achieve timing requirement Clock Setup: 'pll:U3\|altpll:altpll_component\|_clk0' along 283 path(s). See Report window for details." {  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk register image1:U2\|count1\[6\] register rs232_t:u5\|dataout\[1\] -5.601 ns " "Info: Slack time is -5.601 ns for clock \"clk\" between source register \"image1:U2\|count1\[6\]\" and destination register \"rs232_t:u5\|dataout\[1\]\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-4.538 ns + Largest register register " "Info: + Largest register to register requirement is -4.538 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "0.035 ns + " "Info: + Setup relationship between source and destination is 0.035 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.925 ns " "Info: + Latch edge is 0.925 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk 25.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk\" is 25.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.890 ns " "Info: - Launch edge is 0.890 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll:U3\|altpll:altpll_component\|_clk0 18.518 ns -1.885 ns  50 " "Info: Clock period of Source clock \"pll:U3\|altpll:altpll_component\|_clk0\" is 18.518 ns with  offset of -1.885 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.312 ns + Largest " "Info: + Largest clock skew is -4.312 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.905 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.905 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk 1 CLK PIN_17 236 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_17; Fanout = 236; CLK Node = 'clk'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "" { clk } "NODE_NAME" } "" } } { "image.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image.vhd" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.725 ns) + CELL(0.711 ns) 2.905 ns rs232_t:u5\|dataout\[1\] 2 REG LC_X10_Y8_N6 1 " "Info: 2: + IC(0.725 ns) + CELL(0.711 ns) = 2.905 ns; Loc. = LC_X10_Y8_N6; Fanout = 1; REG Node = 'rs232_t:u5\|dataout\[1\]'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "1.436 ns" { clk rs232_t:u5|dataout[1] } "NODE_NAME" } "" } } { "rs232_t.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/rs232_t.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.180 ns 75.04 % " "Info: Total cell delay = 2.180 ns ( 75.04 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.725 ns 24.96 % " "Info: Total interconnect delay = 0.725 ns ( 24.96 % )" {  } {  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.905 ns" { clk rs232_t:u5|dataout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.905 ns" { clk clk~out0 rs232_t:u5|dataout[1] } { 0.000ns 0.000ns 0.725ns } { 0.000ns 1.469ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:U3\|altpll:altpll_component\|_clk0 source 7.217 ns - Longest register " "Info: - Longest clock path from clock \"pll:U3\|altpll:altpll_component\|_clk0\" to source register is 7.217 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:U3\|altpll:altpll_component\|_clk0 1 CLK PLL_1 241 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 241; CLK Node = 'pll:U3\|altpll:altpll_component\|_clk0'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "" { pll:U3|altpll:altpll_component|_clk0 } "NODE_NAME" } "" } } { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.674 ns) + CELL(0.935 ns) 2.609 ns clkx 2 REG LC_X24_Y10_N7 9 " "Info: 2: + IC(1.674 ns) + CELL(0.935 ns) = 2.609 ns; Loc. = LC_X24_Y10_N7; Fanout = 9; REG Node = 'clkx'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.609 ns" { pll:U3|altpll:altpll_component|_clk0 clkx } "NODE_NAME" } "" } } { "image.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.897 ns) + CELL(0.711 ns) 7.217 ns image1:U2\|count1\[6\] 3 REG LC_X11_Y8_N6 4 " "Info: 3: + IC(3.897 ns) + CELL(0.711 ns) = 7.217 ns; Loc. = LC_X11_Y8_N6; Fanout = 4; REG Node = 'image1:U2\|count1\[6\]'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "4.608 ns" { clkx image1:U2|count1[6] } "NODE_NAME" } "" } } { "image1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image1.vhd" 92 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.646 ns 22.81 % " "Info: Total cell delay = 1.646 ns ( 22.81 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.571 ns 77.19 % " "Info: Total interconnect delay = 5.571 ns ( 77.19 % )" {  } {  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "7.217 ns" { pll:U3|altpll:altpll_component|_clk0 clkx image1:U2|count1[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.217 ns" { pll:U3|altpll:altpll_component|_clk0 clkx image1:U2|count1[6] } { 0.000ns 1.674ns 3.897ns } { 0.000ns 0.935ns 0.711ns } } }  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.905 ns" { clk rs232_t:u5|dataout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.905 ns" { clk clk~out0 rs232_t:u5|dataout[1] } { 0.000ns 0.000ns 0.725ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "7.217 ns" { pll:U3|altpll:altpll_component|_clk0 clkx image1:U2|count1[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.217 ns" { pll:U3|altpll:altpll_component|_clk0 clkx image1:U2|count1[6] } { 0.000ns 1.674ns 3.897ns } { 0.000ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" {  } { { "image1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image1.vhd" 92 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns - " "Info: - Micro setup delay of destination is 0.037 ns" {  } { { "rs232_t.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/rs232_t.vhd" 21 -1 0 } }  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.905 ns" { clk rs232_t:u5|dataout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.905 ns" { clk clk~out0 rs232_t:u5|dataout[1] } { 0.000ns 0.000ns 0.725ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "7.217 ns" { pll:U3|altpll:altpll_component|_clk0 clkx image1:U2|count1[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.217 ns" { pll:U3|altpll:altpll_component|_clk0 clkx image1:U2|count1[6] } { 0.000ns 1.674ns 3.897ns } { 0.000ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.063 ns - Longest register register " "Info: - Longest register to register delay is 1.063 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns image1:U2\|count1\[6\] 1 REG LC_X11_Y8_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y8_N6; Fanout = 4; REG Node = 'image1:U2\|count1\[6\]'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "" { image1:U2|count1[6] } "NODE_NAME" } "" } } { "image1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image1.vhd" 92 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.754 ns) + CELL(0.309 ns) 1.063 ns rs232_t:u5\|dataout\[1\] 2 REG LC_X10_Y8_N6 1 " "Info: 2: + IC(0.754 ns) + CELL(0.309 ns) = 1.063 ns; Loc. = LC_X10_Y8_N6; Fanout = 1; REG Node = 'rs232_t:u5\|dataout\[1\]'" {  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "1.063 ns" { image1:U2|count1[6] rs232_t:u5|dataout[1] } "NODE_NAME" } "" } } { "rs232_t.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/rs232_t.vhd" 21 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.309 ns 29.07 % " "Info: Total cell delay = 0.309 ns ( 29.07 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.754 ns 70.93 % " "Info: Total interconnect delay = 0.754 ns ( 70.93 % )" {  } {  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "1.063 ns" { image1:U2|count1[6] rs232_t:u5|dataout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.063 ns" { image1:U2|count1[6] rs232_t:u5|dataout[1] } { 0.000ns 0.754ns } { 0.000ns 0.309ns } } }  } 0}  } { { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "2.905 ns" { clk rs232_t:u5|dataout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "2.905 ns" { clk clk~out0 rs232_t:u5|dataout[1] } { 0.000ns 0.000ns 0.725ns } { 0.000ns 1.469ns 0.711ns } } } { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "7.217 ns" { pll:U3|altpll:altpll_component|_clk0 clkx image1:U2|count1[6] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "7.217 ns" { pll:U3|altpll:altpll_component|_clk0 clkx image1:U2|count1[6] } { 0.000ns 1.674ns 3.897ns } { 0.000ns 0.935ns 0.711ns } } } { "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" "" { Report "D:/study/毕业设计/韩健程序/cyclic/db/image_cmp.qrpt" Compiler "image" "UNKNOWN" "V1" "D:/study/毕业设计/韩健程序/cyclic/db/image.quartus_db" { Floorplan "D:/study/毕业设计/韩健程序/cyclic/" "" "1.063 ns" { image1:U2|count1[6] rs232_t:u5|dataout[1] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "1.063 ns" { image1:U2|count1[6] rs232_t:u5|dataout[1] } { 0.000ns 0.754ns } { 0.000ns 0.309ns } } }  } 0}
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