image.tan.qmsg

FPGA的串口通信程序

{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" {  } {  } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "rs232_r:U1\|rcv:u2\|clkdiv\[3\] " "Info: Detected ripple clock \"rs232_r:U1\|rcv:u2\|clkdiv\[3\]\" as buffer" {  } { { "rcv.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/rcv.vhd" 33 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rs232_r:U1\|rcv:u2\|clkdiv\[3\]" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "clkx " "Info: Detected ripple clock \"clkx\" as buffer" {  } { { "image.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image.vhd" 30 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkx" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "rs232_t:u5\|pll1:u1\|c0 " "Info: Detected ripple clock \"rs232_t:u5\|pll1:u1\|c0\" as buffer" {  } { { "pll1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/pll1.vhd" 12 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rs232_t:u5\|pll1:u1\|c0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "rs232_t:u5\|send:u2\|clk1x_enable " "Info: Detected ripple clock \"rs232_t:u5\|send:u2\|clk1x_enable\" as buffer" {  } { { "send.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/send.vhd" 18 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rs232_t:u5\|send:u2\|clk1x_enable" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "rs232_r:U1\|pll1:u1\|c0 " "Info: Detected ripple clock \"rs232_r:U1\|pll1:u1\|c0\" as buffer" {  } { { "pll1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/pll1.vhd" 12 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rs232_r:U1\|pll1:u1\|c0" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "rs232_t:u5\|send:u2\|clkdiv\[3\] " "Info: Detected ripple clock \"rs232_t:u5\|send:u2\|clkdiv\[3\]\" as buffer" {  } { { "send.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/send.vhd" 21 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "rs232_t:u5\|send:u2\|clkdiv\[3\]" } } } }  } 0}  } {  } 0}
{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0}