image.map.qmsg

FPGA的串口通信程序

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rs232_r:U1\|rcv:u2\|panel\[1\] data_in GND " "Warning: Reduced register \"rs232_r:U1\|rcv:u2\|panel\[1\]\" with stuck data_in port to stuck value GND" {  } { { "rcv.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/rcv.vhd" 23 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rs232_r:U1\|rcv:u2\|rgb_sel\[1\] data_in GND " "Warning: Reduced register \"rs232_r:U1\|rcv:u2\|rgb_sel\[1\]\" with stuck data_in port to stuck value GND" {  } { { "rcv.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/rcv.vhd" 12 -1 0 } }  } 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "rs232_r:U1\|rcv:u2\|rgb_sel\[0\] High " "Info: Power-up level of register \"rs232_r:U1\|rcv:u2\|rgb_sel\[0\]\" is not specified -- using power-up level of High to minimize register" {  } { { "rcv.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/rcv.vhd" 12 -1 0 } }  } 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "rs232_r:U1\|rcv:u2\|rgb_sel\[0\] data_in VCC " "Warning: Reduced register \"rs232_r:U1\|rcv:u2\|rgb_sel\[0\]\" with stuck data_in port to stuck value VCC" {  } { { "rcv.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/rcv.vhd" 12 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT" "\|image\|image1:U2\|shinningblock:U2\|state 4 0 " "Info: State machine \"\|image\|image1:U2\|shinningblock:U2\|state\" contains 4 states and 0 state bits" {  } { { "shinningblock.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/shinningblock.vhd" 48 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|image\|image1:U2\|shinningblock:U2\|state " "Info: Selected Auto state machine encoding method for state machine \"\|image\|image1:U2\|shinningblock:U2\|state\"" {  } { { "shinningblock.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/shinningblock.vhd" 48 -1 0 } }  } 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|image\|image1:U2\|shinningblock:U2\|state " "Info: Encoding result for state machine \"\|image\|image1:U2\|shinningblock:U2\|state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "4 " "Info: Completed encoding using 4 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "image1:U2\|shinningblock:U2\|state.state3 " "Info: Encoded state bit \"image1:U2\|shinningblock:U2\|state.state3\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "image1:U2\|shinningblock:U2\|state.state2 " "Info: Encoded state bit \"image1:U2\|shinningblock:U2\|state.state2\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "image1:U2\|shinningblock:U2\|state.state1 " "Info: Encoded state bit \"image1:U2\|shinningblock:U2\|state.state1\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "image1:U2\|shinningblock:U2\|state.tristate " "Info: Encoded state bit \"image1:U2\|shinningblock:U2\|state.tristate\"" {  } {  } 0}  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|image\|image1:U2\|shinningblock:U2\|state.tristate 0000 " "Info: State \"\|image\|image1:U2\|shinningblock:U2\|state.tristate\" uses code string \"0000\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|image\|image1:U2\|shinningblock:U2\|state.state1 0011 " "Info: State \"\|image\|image1:U2\|shinningblock:U2\|state.state1\" uses code string \"0011\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|image\|image1:U2\|shinningblock:U2\|state.state2 0101 " "Info: State \"\|image\|image1:U2\|shinningblock:U2\|state.state2\" uses code string \"0101\"" {  } {  } 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|image\|image1:U2\|shinningblock:U2\|state.state3 1001 " "Info: State \"\|image\|image1:U2\|shinningblock:U2\|state.state3\" uses code string \"1001\"" {  } {  } 0}  } { { "shinningblock.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/shinningblock.vhd" 48 -1 0 } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "rs232_r:U1\|pll1:u1\|number\[1\] rs232_t:u5\|pll1:u1\|number\[1\] " "Info: Duplicate register \"rs232_r:U1\|pll1:u1\|number\[1\]\" merged to single register \"rs232_t:u5\|pll1:u1\|number\[1\]\"" {  } { { "pll1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/pll1.vhd" 18 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "pixs_out VCC " "Warning: Pin \"pixs_out\" stuck at VCC" {  } { { "image.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image.vhd" 14 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WCUT_CUT_YGR_PLL_BAD_FANOUT_CLK3" "clk0 pll:U3\|altpll:altpll_component\|pll " "Warning: Output port clk0 of PLL \"pll:U3\|altpll:altpll_component\|pll\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance." {  } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 763 3 0 } } { "pll.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/pll.vhd" 86 -1 0 } } { "image.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image.vhd" 123 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "1100 " "Info: Implemented 1100 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "58 " "Info: Implemented 58 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_BIDIRS" "1 " "Info: Implemented 1 bidirectional pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "1039 " "Info: Implemented 1039 logic cells" {  } {  } 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 27 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 27 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 21 09:41:16 2008 " "Info: Processing ended: Mon Apr 21 09:41:16 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:18 " "Info: Elapsed time: 00:00:18" {  } {  } 0}  } {  } 0}