image.map.qmsg

FPGA的串口通信程序

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus50/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus50/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altpll.tdf" 363 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pll:U3\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"pll:U3\|altpll:altpll_component\"" {  } { { "pll.vhd" "altpll_component" { Text "D:/study/毕业设计/韩健程序/cyclic/pll.vhd" 86 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "amp amp:U4 " "Info: Elaborating entity \"amp\" for hierarchy \"amp:U4\"" {  } { { "image.vhd" "U4" { Text "D:/study/毕业设计/韩健程序/cyclic/image.vhd" 130 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "count amp:U4\|count:U1 " "Info: Elaborating entity \"count\" for hierarchy \"amp:U4\|count:U1\"" {  } { { "amp.vhd" "U1" { Text "D:/study/毕业设计/韩健程序/cyclic/amp.vhd" 43 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rs232_t rs232_t:u5 " "Info: Elaborating entity \"rs232_t\" for hierarchy \"rs232_t:u5\"" {  } { { "image.vhd" "u5" { Text "D:/study/毕业设计/韩健程序/cyclic/image.vhd" 141 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll1 rs232_t:u5\|pll1:u1 " "Info: Elaborating entity \"pll1\" for hierarchy \"rs232_t:u5\|pll1:u1\"" {  } { { "rs232_t.vhd" "u1" { Text "D:/study/毕业设计/韩健程序/cyclic/rs232_t.vhd" 58 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "send rs232_t:u5\|send:u2 " "Info: Elaborating entity \"send\" for hierarchy \"rs232_t:u5\|send:u2\"" {  } { { "rs232_t.vhd" "u2" { Text "D:/study/毕业设计/韩健程序/cyclic/rs232_t.vhd" 59 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rs232_r rs232_r:U1 " "Info: Elaborating entity \"rs232_r\" for hierarchy \"rs232_r:U1\"" {  } { { "image.vhd" "U1" { Text "D:/study/毕业设计/韩健程序/cyclic/image.vhd" 150 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rcv rs232_r:U1\|rcv:u2 " "Info: Elaborating entity \"rcv\" for hierarchy \"rs232_r:U1\|rcv:u2\"" {  } { { "rs232_r.vhd" "u2" { Text "D:/study/毕业设计/韩健程序/cyclic/rs232_r.vhd" 59 -1 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "image1 image1:U2 " "Info: Elaborating entity \"image1\" for hierarchy \"image1:U2\"" {  } { { "image.vhd" "U2" { Text "D:/study/毕业设计/韩健程序/cyclic/image.vhd" 171 -1 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "data_g image1.vhd(65) " "Info: (10035) Verilog HDL or VHDL information at image1.vhd(65): object \"data_g\" declared but not used" {  } { { "image1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image1.vhd" 65 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "data_b image1.vhd(66) " "Info: (10035) Verilog HDL or VHDL information at image1.vhd(66): object \"data_b\" declared but not used" {  } { { "image1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image1.vhd" 66 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "levelin1 image1.vhd(88) " "Info: (10035) Verilog HDL or VHDL information at image1.vhd(88): object \"levelin1\" declared but not used" {  } { { "image1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image1.vhd" 88 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "levelin2 image1.vhd(89) " "Info: (10035) Verilog HDL or VHDL information at image1.vhd(89): object \"levelin2\" declared but not used" {  } { { "image1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image1.vhd" 89 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "shinningblock image1:U2\|shinningblock:U2 " "Info: Elaborating entity \"shinningblock\" for hierarchy \"image1:U2\|shinningblock:U2\"" {  } { { "image1.vhd" "U2" { Text "D:/study/毕业设计/韩健程序/cyclic/image1.vhd" 375 -1 0 } }  } 0}
{ "Info" "IVRFX_VHDL_CASE_STATEMENT_OTHERS_CLAUSE_NEVER_SELECTED" "shinningblock.vhd(292) " "Info: VHDL Case Statement information at shinningblock.vhd(292): OTHERS choice is never selected" {  } { { "shinningblock.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/shinningblock.vhd" 292 0 0 } }  } 0}