image.map.qmsg

FPGA的串口通信程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 21 09:40:58 2008 " "Info: Processing started: Mon Apr 21 09:40:58 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off image -c image " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off image -c image" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "image.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file image.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 image-rtl " "Info: Found design unit 1: image-rtl" {  } { { "image.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image.vhd" 28 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 image " "Info: Found entity 1: image" {  } { { "image.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image.vhd" 6 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "image1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file image1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 image1-rtl " "Info: Found design unit 1: image1-rtl" {  } { { "image1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image1.vhd" 43 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 image1 " "Info: Found entity 1: image1" {  } { { "image1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/image1.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "shinningblock.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file shinningblock.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 shinningblock-rtl " "Info: Found design unit 1: shinningblock-rtl" {  } { { "shinningblock.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/shinningblock.vhd" 41 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 shinningblock " "Info: Found entity 1: shinningblock" {  } { { "shinningblock.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/shinningblock.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rs232_r.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rs232_r.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rs232_r-rtl " "Info: Found design unit 1: rs232_r-rtl" {  } { { "rs232_r.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/rs232_r.vhd" 26 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 rs232_r " "Info: Found entity 1: rs232_r" {  } { { "rs232_r.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/rs232_r.vhd" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pll1.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file pll1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pll1-counter " "Info: Found design unit 1: pll1-counter" {  } { { "pll1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/pll1.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 pll1 " "Info: Found entity 1: pll1" {  } { { "pll1.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/pll1.vhd" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rcv.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rcv.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rcv-v1 " "Info: Found design unit 1: rcv-v1" {  } { { "rcv.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/rcv.vhd" 28 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 rcv " "Info: Found entity 1: rcv" {  } { { "rcv.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/rcv.vhd" 10 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "amp.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file amp.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 amp-rtl " "Info: Found design unit 1: amp-rtl" {  } { { "amp.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/amp.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 amp " "Info: Found entity 1: amp" {  } { { "amp.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/amp.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "count.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file count.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count-rtl " "Info: Found design unit 1: count-rtl" {  } { { "count.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/count.vhd" 15 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 count " "Info: Found entity 1: count" {  } { { "count.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/count.vhd" 7 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rs232_t.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file rs232_t.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 rs232_t-rtl " "Info: Found design unit 1: rs232_t-rtl" {  } { { "rs232_t.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/rs232_t.vhd" 18 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 rs232_t " "Info: Found entity 1: rs232_t" {  } { { "rs232_t.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/rs232_t.vhd" 8 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "send.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file send.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 send-rtl " "Info: Found design unit 1: send-rtl" {  } { { "send.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/send.vhd" 16 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 send " "Info: Found entity 1: send" {  } { { "send.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/send.vhd" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "image " "Info: Elaborating entity \"image\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "pll.vhd 2 1 " "Info: Using design file pll.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pll-SYN " "Info: Found design unit 1: pll-SYN" {  } { { "pll.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/pll.vhd" 48 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 pll " "Info: Found entity 1: pll" {  } { { "pll.vhd" "" { Text "D:/study/毕业设计/韩健程序/cyclic/pll.vhd" 39 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll pll:U3 " "Info: Elaborating entity \"pll\" for hierarchy \"pll:U3\"" {  } { { "image.vhd" "U3" { Text "D:/study/毕业设计/韩健程序/cyclic/image.vhd" 123 -1 0 } }  } 0}