image.hier_info

FPGA的串口通信程序

|image|rs232_t:u5|pll1:u1
inclk0 => number[7].CLK
inclk0 => number[6].CLK
inclk0 => number[5].CLK
inclk0 => number[4].CLK
inclk0 => number[3].CLK
inclk0 => number[2].CLK
inclk0 => number[1].CLK
inclk0 => number[0].CLK
inclk0 => c0~reg0.CLK
inclk0 => number[8].CLK
c0 <= c0~reg0.DB_MAX_OUTPUT_PORT_TYPE


|image|rs232_t:u5|send:u2
clk16x => clkdiv[2].CLK
clk16x => clkdiv[1].CLK
clk16x => clkdiv[0].CLK
clk16x => clkdiv[3].CLK
clk => clk1x_enable.CLK
ctrl => clk1x_enable~1.OUTPUTSELECT
datain[0] => tbr[0].DATAIN
datain[1] => tbr[1].DATAIN
datain[2] => tbr[2].DATAIN
datain[3] => tbr[3].DATAIN
datain[4] => tbr[4].DATAIN
datain[5] => tbr[5].DATAIN
datain[6] => tbr[6].DATAIN
datain[7] => tbr[7].DATAIN
dout <= dout~reg0.DB_MAX_OUTPUT_PORT_TYPE


|image|rs232_r:U1
inclk => pll1:u1.inclk0
rxd => rcv:u2.rxd
rgb_sel[0] <= rcv:u2.rgb_sel[0]
rgb_sel[1] <= rcv:u2.rgb_sel[1]
rgb_sel[2] <= rcv:u2.rgb_sel[2]
rgb_sel[3] <= rcv:u2.rgb_sel[3]
rgb_sel[4] <= rcv:u2.rgb_sel[4]
rgb_sel[5] <= rcv:u2.rgb_sel[5]
rgb_sel[6] <= rcv:u2.rgb_sel[6]
rgb_sel[7] <= rcv:u2.rgb_sel[7]
level1[0] <= rcv:u2.level1[0]
level1[1] <= rcv:u2.level1[1]
level1[2] <= rcv:u2.level1[2]
level1[3] <= rcv:u2.level1[3]
level1[4] <= rcv:u2.level1[4]
level1[5] <= rcv:u2.level1[5]
level1[6] <= rcv:u2.level1[6]
level1[7] <= rcv:u2.level1[7]
level2[0] <= rcv:u2.level2[0]
level2[1] <= rcv:u2.level2[1]
level2[2] <= rcv:u2.level2[2]
level2[3] <= rcv:u2.level2[3]
level2[4] <= rcv:u2.level2[4]
level2[5] <= rcv:u2.level2[5]
level2[6] <= rcv:u2.level2[6]
level2[7] <= rcv:u2.level2[7]
level3[0] <= rcv:u2.level3[0]
level3[1] <= rcv:u2.level3[1]
level3[2] <= rcv:u2.level3[2]
level3[3] <= rcv:u2.level3[3]
level3[4] <= rcv:u2.level3[4]
level3[5] <= rcv:u2.level3[5]
level3[6] <= rcv:u2.level3[6]
level3[7] <= rcv:u2.level3[7]
time1[0] <= rcv:u2.time1[0]
time1[1] <= rcv:u2.time1[1]
time1[2] <= rcv:u2.time1[2]
time1[3] <= rcv:u2.time1[3]
time1[4] <= rcv:u2.time1[4]
time1[5] <= rcv:u2.time1[5]
time1[6] <= rcv:u2.time1[6]
time1[7] <= rcv:u2.time1[7]
time2[0] <= rcv:u2.time2[0]
time2[1] <= rcv:u2.time2[1]
time2[2] <= rcv:u2.time2[2]
time2[3] <= rcv:u2.time2[3]
time2[4] <= rcv:u2.time2[4]
time2[5] <= rcv:u2.time2[5]
time2[6] <= rcv:u2.time2[6]
time2[7] <= rcv:u2.time2[7]
time3[0] <= rcv:u2.time3[0]
time3[1] <= rcv:u2.time3[1]
time3[2] <= rcv:u2.time3[2]
time3[3] <= rcv:u2.time3[3]
time3[4] <= rcv:u2.time3[4]
time3[5] <= rcv:u2.time3[5]
time3[6] <= rcv:u2.time3[6]
time3[7] <= rcv:u2.time3[7]
panel_sel[0] <= rcv:u2.panel_sel[0]
panel_sel[1] <= rcv:u2.panel_sel[1]
panel_sel[2] <= rcv:u2.panel_sel[2]
panel_sel[3] <= rcv:u2.panel_sel[3]
panel_sel[4] <= rcv:u2.panel_sel[4]
panel_sel[5] <= rcv:u2.panel_sel[5]
panel_sel[6] <= rcv:u2.panel_sel[6]
panel_sel[7] <= rcv:u2.panel_sel[7]
auto[0] <= rcv:u2.auto[0]
auto[1] <= rcv:u2.auto[1]
auto[2] <= rcv:u2.auto[2]
auto[3] <= rcv:u2.auto[3]
auto[4] <= rcv:u2.auto[4]
auto[5] <= rcv:u2.auto[5]
auto[6] <= rcv:u2.auto[6]
auto[7] <= rcv:u2.auto[7]
levellow[0] <= rcv:u2.levellow[0]
levellow[1] <= rcv:u2.levellow[1]
levellow[2] <= rcv:u2.levellow[2]
levellow[3] <= rcv:u2.levellow[3]
levellow[4] <= rcv:u2.levellow[4]
levellow[5] <= rcv:u2.levellow[5]
levellow[6] <= rcv:u2.levellow[6]
levellow[7] <= rcv:u2.levellow[7]
levelhigh[0] <= rcv:u2.levelhigh[0]
levelhigh[1] <= rcv:u2.levelhigh[1]
levelhigh[2] <= rcv:u2.levelhigh[2]
levelhigh[3] <= rcv:u2.levelhigh[3]
levelhigh[4] <= rcv:u2.levelhigh[4]
levelhigh[5] <= rcv:u2.levelhigh[5]
levelhigh[6] <= rcv:u2.levelhigh[6]
levelhigh[7] <= rcv:u2.levelhigh[7]
panel[0] <= rcv:u2.panel[0]
panel[1] <= rcv:u2.panel[1]
panel[2] <= rcv:u2.panel[2]
panel[3] <= rcv:u2.panel[3]
panel[4] <= rcv:u2.panel[4]
panel[5] <= rcv:u2.panel[5]
panel[6] <= rcv:u2.panel[6]
panel[7] <= rcv:u2.panel[7]
amp[0] <= rcv:u2.amp[0]
amp[1] <= rcv:u2.amp[1]
amp[2] <= rcv:u2.amp[2]
amp[3] <= rcv:u2.amp[3]
amp[4] <= rcv:u2.amp[4]
amp[5] <= rcv:u2.amp[5]
amp[6] <= rcv:u2.amp[6]
amp[7] <= rcv:u2.amp[7]


|image|rs232_r:U1|pll1:u1
inclk0 => number[7].CLK
inclk0 => number[6].CLK
inclk0 => number[5].CLK
inclk0 => number[4].CLK
inclk0 => number[3].CLK
inclk0 => number[2].CLK
inclk0 => number[1].CLK
inclk0 => number[0].CLK
inclk0 => c0~reg0.CLK
inclk0 => number[8].CLK
c0 <= c0~reg0.DB_MAX_OUTPUT_PORT_TYPE


|image|rs232_r:U1|rcv:u2
clk16x => rxd1.CLK
clk16x => clk1x_enable.CLK
clk16x => clkdiv[3].CLK
clk16x => clkdiv[2].CLK
clk16x => clkdiv[1].CLK
clk16x => clkdiv[0].CLK
clk16x => rgb_sel[7]~reg0.CLK
clk16x => rgb_sel[6]~reg0.CLK
clk16x => rgb_sel[5]~reg0.CLK
clk16x => rgb_sel[4]~reg0.CLK
clk16x => rgb_sel[3]~reg0.CLK
clk16x => rgb_sel[2]~reg0.CLK
clk16x => rgb_sel[1]~reg0.CLK
clk16x => rgb_sel[0]~reg0.CLK
clk16x => level1[7]~reg0.CLK
clk16x => level1[6]~reg0.CLK
clk16x => level1[5]~reg0.CLK
clk16x => level1[4]~reg0.CLK
clk16x => level1[3]~reg0.CLK
clk16x => level1[2]~reg0.CLK
clk16x => level1[1]~reg0.CLK
clk16x => level1[0]~reg0.CLK
clk16x => level2[7]~reg0.CLK
clk16x => level2[6]~reg0.CLK
clk16x => level2[5]~reg0.CLK
clk16x => level2[4]~reg0.CLK
clk16x => level2[3]~reg0.CLK
clk16x => level2[2]~reg0.CLK
clk16x => level2[1]~reg0.CLK
clk16x => level2[0]~reg0.CLK
clk16x => level3[7]~reg0.CLK
clk16x => level3[6]~reg0.CLK
clk16x => level3[5]~reg0.CLK
clk16x => level3[4]~reg0.CLK
clk16x => level3[3]~reg0.CLK
clk16x => level3[2]~reg0.CLK
clk16x => level3[1]~reg0.CLK
clk16x => level3[0]~reg0.CLK
clk16x => time1[7]~reg0.CLK
clk16x => time1[6]~reg0.CLK
clk16x => time1[5]~reg0.CLK
clk16x => time1[4]~reg0.CLK
clk16x => time1[3]~reg0.CLK
clk16x => time1[2]~reg0.CLK
clk16x => time1[1]~reg0.CLK
clk16x => time1[0]~reg0.CLK
clk16x => time2[7]~reg0.CLK
clk16x => time2[6]~reg0.CLK
clk16x => time2[5]~reg0.CLK
clk16x => time2[4]~reg0.CLK
clk16x => time2[3]~reg0.CLK
clk16x => time2[2]~reg0.CLK
clk16x => time2[1]~reg0.CLK
clk16x => time2[0]~reg0.CLK
clk16x => time3[7]~reg0.CLK
clk16x => time3[6]~reg0.CLK
clk16x => time3[5]~reg0.CLK
clk16x => time3[4]~reg0.CLK
clk16x => time3[3]~reg0.CLK
clk16x => time3[2]~reg0.CLK
clk16x => time3[1]~reg0.CLK
clk16x => time3[0]~reg0.CLK
clk16x => panel_sel[7]~reg0.CLK
clk16x => panel_sel[6]~reg0.CLK
clk16x => panel_sel[5]~reg0.CLK
clk16x => panel_sel[4]~reg0.CLK
clk16x => panel_sel[3]~reg0.CLK
clk16x => panel_sel[2]~reg0.CLK
clk16x => panel_sel[1]~reg0.CLK
clk16x => panel_sel[0]~reg0.CLK
clk16x => auto[7]~reg0.CLK
clk16x => auto[6]~reg0.CLK
clk16x => auto[5]~reg0.CLK
clk16x => auto[4]~reg0.CLK
clk16x => auto[3]~reg0.CLK
clk16x => auto[2]~reg0.CLK
clk16x => auto[1]~reg0.CLK
clk16x => auto[0]~reg0.CLK
clk16x => levellow[7]~reg0.CLK
clk16x => levellow[6]~reg0.CLK
clk16x => levellow[5]~reg0.CLK
clk16x => levellow[4]~reg0.CLK
clk16x => levellow[3]~reg0.CLK
clk16x => levellow[2]~reg0.CLK
clk16x => levellow[1]~reg0.CLK
clk16x => levellow[0]~reg0.CLK
clk16x => levelhigh[7]~reg0.CLK
clk16x => levelhigh[6]~reg0.CLK
clk16x => levelhigh[5]~reg0.CLK
clk16x => levelhigh[4]~reg0.CLK
clk16x => levelhigh[3]~reg0.CLK
clk16x => levelhigh[2]~reg0.CLK
clk16x => levelhigh[1]~reg0.CLK
clk16x => levelhigh[0]~reg0.CLK
clk16x => panel[7]~reg0.CLK
clk16x => panel[6]~reg0.CLK
clk16x => panel[5]~reg0.CLK
clk16x => panel[4]~reg0.CLK
clk16x => panel[3]~reg0.CLK
clk16x => panel[2]~reg0.CLK
clk16x => panel[1]~reg0.CLK
clk16x => panel[0]~reg0.CLK
clk16x => amp[7]~reg0.CLK
clk16x => amp[6]~reg0.CLK
clk16x => amp[5]~reg0.CLK
clk16x => amp[4]~reg0.CLK
clk16x => amp[3]~reg0.CLK
clk16x => amp[2]~reg0.CLK
clk16x => amp[1]~reg0.CLK
clk16x => amp[0]~reg0.CLK
clk16x => rxd2.CLK
rxd => rxd1.DATAIN
rxd => process1~0.IN1
rgb_sel[0] <= rgb_sel[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rgb_sel[1] <= rgb_sel[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rgb_sel[2] <= rgb_sel[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rgb_sel[3] <= rgb_sel[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rgb_sel[4] <= rgb_sel[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rgb_sel[5] <= rgb_sel[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rgb_sel[6] <= rgb_sel[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rgb_sel[7] <= rgb_sel[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level1[0] <= level1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level1[1] <= level1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level1[2] <= level1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level1[3] <= level1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level1[4] <= level1[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level1[5] <= level1[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level1[6] <= level1[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level1[7] <= level1[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level2[0] <= level2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level2[1] <= level2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level2[2] <= level2[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level2[3] <= level2[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level2[4] <= level2[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level2[5] <= level2[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level2[6] <= level2[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level2[7] <= level2[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level3[0] <= level3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level3[1] <= level3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level3[2] <= level3[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level3[3] <= level3[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level3[4] <= level3[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level3[5] <= level3[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level3[6] <= level3[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
level3[7] <= level3[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time1[0] <= time1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time1[1] <= time1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time1[2] <= time1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time1[3] <= time1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time1[4] <= time1[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time1[5] <= time1[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time1[6] <= time1[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time1[7] <= time1[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time2[0] <= time2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time2[1] <= time2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time2[2] <= time2[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time2[3] <= time2[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time2[4] <= time2[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time2[5] <= time2[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time2[6] <= time2[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time2[7] <= time2[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time3[0] <= time3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time3[1] <= time3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time3[2] <= time3[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time3[3] <= time3[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time3[4] <= time3[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time3[5] <= time3[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time3[6] <= time3[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
time3[7] <= time3[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
panel_sel[0] <= panel_sel[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
panel_sel[1] <= panel_sel[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
panel_sel[2] <= panel_sel[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
panel_sel[3] <= panel_sel[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
panel_sel[4] <= panel_sel[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
panel_sel[5] <= panel_sel[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
panel_sel[6] <= panel_sel[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
panel_sel[7] <= panel_sel[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
auto[0] <= auto[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
auto[1] <= auto[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
auto[2] <= auto[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
auto[3] <= auto[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
auto[4] <= auto[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
auto[5] <= auto[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
auto[6] <= auto[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
auto[7] <= auto[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
levellow[0] <= levellow[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
levellow[1] <= levellow[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
levellow[2] <= levellow[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
levellow[3] <= levellow[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
levellow[4] <= levellow[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
levellow[5] <= levellow[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
levellow[6] <= levellow[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
levellow[7] <= levellow[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
levelhigh[0] <= levelhigh[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
levelhigh[1] <= levelhigh[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
levelhigh[2] <= levelhigh[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
levelhigh[3] <= levelhigh[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
levelhigh[4] <= levelhigh[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
levelhigh[5] <= levelhigh[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
levelhigh[6] <= levelhigh[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
levelhigh[7] <= levelhigh[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
panel[0] <= panel[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
panel[1] <= panel[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
panel[2] <= panel[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
panel[3] <= panel[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
panel[4] <= panel[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
panel[5] <= panel[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
panel[6] <= panel[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
panel[7] <= panel[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
amp[0] <= amp[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
amp[1] <= amp[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
amp[2] <= amp[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
amp[3] <= amp[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
amp[4] <= amp[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
amp[5] <= amp[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
amp[6] <= amp[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
amp[7] <= amp[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|image|image1:U2
clk => mode.CLK
clk => outsel.CLK
clk => time1in[3].CLK
clk => time1in[2].CLK
clk => time1in[1].CLK
clk => time1in[0].CLK
clk => time2in[3].CLK
clk => time2in[2].CLK
clk => time2in[1].CLK
clk => time2in[0].CLK
clk => time3in[3].CLK
clk => time3in[2].CLK
clk => time3in[1].CLK
clk => time3in[0].CLK
clk => size[3].CLK
clk => size[2].CLK
clk => size[1].CLK
clk => size[0].CLK
clk => level1in[7].CLK
clk => level1in[6].CLK
clk => level1in[5].CLK
clk => level1in[4].CLK
clk => level1in[3].CLK
clk => level1in[2].CLK
clk => level1in[1].CLK
clk => level1in[0].CLK
clk => level2in[7].CLK
clk => level2in[6].CLK
clk => level2in[5].CLK
clk => level2in[4].CLK
clk => level2in[3].CLK
clk => level2in[2].CLK
clk => level2in[1].CLK
clk => level2in[0].CLK
clk => chose[2].CLK
clk => chose[1].CLK
clk => chose[0].CLK
clk => refresh[1].CLK
clk => refresh[0].CLK
clk => level3in[7].CLK
clk => level3in[6].CLK
clk => level3in[5].CLK
clk => level3in[4].CLK
clk => level3in[3].CLK
clk => level3in[2].CLK
clk => level3in[1].CLK
clk => level3in[0].CLK
clk => pos[3].CLK
clk => pos[2].CLK
clk => pos[1].CLK
clk => pos[0].CLK
clk => time1set[3].CLK
clk => time1set[2].CLK
clk => time1set[1].CLK