rcv.vhd

FPGA的串口通信程序

--collect the signal from rs232
--two send buttons in the VC++ interface
--send panel button means the parameters of the panel
--send amp button means the parameters to control the amplifier

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;

entity rcv is
port (clk16x,rxd : 		  in std_logic ;
	  rgb_sel 	: 		  out std_logic_vector (7 downto 0);
	  level1 	: 		  out std_logic_vector (7 downto 0);
      level2	:  		  out std_logic_vector (7 downto 0);
	  level3	: 		  out std_logic_vector (7 downto 0);
      time1		:  		  out std_logic_vector (7 downto 0);
	  time2		:		  out std_logic_vector (7 downto 0);
	  time3		:	 	  out std_logic_vector (7 downto 0);
	  panel_sel	:		  out std_logic_vector (7 downto 0);	--图像控制
	  auto	 	:		  out std_logic_vector (7 downto 0);
	  levellow	:		  out std_logic_vector (7 downto 0);	
	  levelhigh :		  out std_logic_vector (7 downto 0);	--自动测量
	  panel		:		  out std_logic_vector (7 downto 0);
	  amp		: 		  out std_logic_vector (7 downto 0)		--光电放大器控制
) ;
end rcv;						

architecture v1 of rcv is

signal rxd1 : std_logic ;
signal rxd2 : std_logic ;
signal clk1x_enable : std_logic ;
signal clkdiv :  unsigned (3 downto 0) ;
signal rsr : unsigned (77 downto 0) ;
signal rbr : unsigned (77 downto 0) ;
signal no_bits_rcvd : unsigned (6 downto 0) ;
signal clk1x : std_logic ;

begin

process (clk16x)
begin
if clk16x'event and clk16x = '1' then
rxd2 <= rxd1 ;
rxd1 <= rxd ;
end if ;
end process ;


process (clk16x,rxd,rxd2,no_bits_rcvd)					--使能信号，保证数据采集时的准确性
begin
if std_logic_vector(no_bits_rcvd) = "1010000" then
clk1x_enable <= '0' ;
elsif clk16x'event and clk16x = '1' then
if rxd = '0' and rxd2 = '1' then
clk1x_enable <= '1' ;
end if ;
end if ;
end process  ;								--clk1x_enable与no_bits_received配合使用


process (clk16x,clk1x_enable)
begin
if clk16x'event and clk16x = '1' then
if std_logic_vector(clkdiv) = "1111" then
clkdiv <= "0000" ;
elsif clk1x_enable = '1' then
clkdiv <= clkdiv + "0001" ;
end if ;
end if ;
end process ;

clk1x <= clkdiv(3) ;						--clk16x是rs232发送波特率的16倍，在每一个bit的中间位置对信号进行采集

process (clk1x)
begin
if clk1x'event and clk1x = '1' then
if std_logic_vector(no_bits_rcvd) >= "0000001" and std_logic_vector(no_bits_rcvd) <= "1001110" then
rsr(0) <= rxd2 ;
rsr(77 downto 1) <= rsr(76 downto 0) ;

elsif std_logic_vector(no_bits_rcvd) = "1001111" then
rbr <= rsr ;								--采集出数据储存进寄存器rsr
end if ;
end if ;
end process ;

process (clk1x,clk1x_enable,no_bits_rcvd)
begin
if (std_logic_vector(no_bits_rcvd) = "1010000" and clk1x_enable = '0') then
no_bits_rcvd <= "0000000" ;
elsif clk1x'event and clk1x = '1' then
if clk1x_enable = '1' then
no_bits_rcvd <= no_bits_rcvd + "0000001" ;		--采集时间段的确立，每次采集rs2328个数据
end if ;
end if ;
end process ;

process(clk16x)
begin
if clk16x'event and clk16x = '1' then
case rbr(71 downto 70) is
when "01" =>									--确认每8个bit数据的最高两位，以得出所接受信号是属于哪个控制信号
		rgb_sel   <= std_logic_vector(rbr(77 downto 70));
		level1    <= std_logic_vector(rbr(67 downto 60));
		level2    <= std_logic_vector(rbr(57 downto 50));
		level3 	  <= std_logic_vector(rbr(47 downto 40));
		time1 	  <= std_logic_vector(rbr(37 downto 30));
		time2 	  <= std_logic_vector(rbr(27 downto 20));
		time3 	  <= std_logic_vector(rbr(17 downto 10));
		panel_sel <= std_logic_vector(rbr(7 downto 0));
		auto	  <= "00000000";				--RGB_SEL前两位为10说明发送来的数据属于图像源（要求rgb_sel数据必须在128与191之间）
		levellow  <= "00000000";
		levelhigh <= "00000000";
when "00" =>
		panel	  <= std_logic_vector(rbr(77 downto 70));
		amp	  	  <= std_logic_vector(rbr(67 downto 60));	--panel前两位为00说明数据属于放大器参数（要求panel数据必须在0与63之间）
when "10" =>
		auto 	  <= "00000010";
		levellow  <= std_logic_vector(rbr(67 downto 60));
		levelhigh <= std_logic_vector(rbr(57 downto 50));	--auto前两位为10说明数据属于自动测量参数（要求panel数据必须在64与127之间）
when others =>
		auto	  <= "00000000";					
		levellow  <= "00000000";								
	    levelhigh <= "00000000";				
end case;
end if;
end process;

end ;