rs232_r.vhd

FPGA的串口通信程序

--the rs232 collection module
--include one clk and one collect component

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;

entity rs232_r is										--rvc and pll1的物理连接
port (inclk, rxd 	: in std_logic ;
   	  rgb_sel 		: out std_logic_vector (7 downto 0);
	  level1  		: out std_logic_vector (7 downto 0);
	  level2  		: out std_logic_vector (7 downto 0);
	  level3  		: out std_logic_vector (7 downto 0);
	  time1   		: out std_logic_vector (7 downto 0);
	  time2   		: out std_logic_vector (7 downto 0);
	  time3   		: out std_logic_vector (7 downto 0);
	  panel_sel		: out std_logic_vector (7 downto 0);
	  auto			: out std_logic_vector (7 downto 0);
	  levellow		: out std_logic_vector (7 downto 0);
	  levelhigh		: out std_logic_vector (7 downto 0);
	  panel   		: out std_logic_vector (7 downto 0);
	  amp	    	: out std_logic_vector (7 downto 0)
) ;
end rs232_r ;

architecture rtl of rs232_r is

signal clk : std_logic ;

component pll1
PORT
(
	inclk0		: IN STD_LOGIC  := '0';
	c0			: OUT STD_LOGIC 
);
END component;

component rcv
port (clk16x,rxd :  in std_logic ;
	  rgb_sel 	 : 	out std_logic_vector (7 downto 0);
	  level1	 : 	out std_logic_vector (7 downto 0);
	  level2	 :  out std_logic_vector (7 downto 0);
	  level3 	 : 	out std_logic_vector (7 downto 0);
	  time1		 :  out std_logic_vector (7 downto 0);
	  time2		 : 	out std_logic_vector (7 downto 0);
	  time3		 : 	out std_logic_vector (7 downto 0);
	  panel_sel  :	out std_logic_vector (7 downto 0);
	  auto		 :	out std_logic_vector (7 downto 0);
	  levellow	 :	out std_logic_vector (7 downto 0);	
	  levelhigh  :	out std_logic_vector (7 downto 0);	--自动测量
	  panel		 : 	out std_logic_vector (7 downto 0);
	  amp		 :	out std_logic_vector (7 downto 0)
) ;
end component;

begin

u1 : pll1 port map (inclk, clk);
u2 : rcv 
port map
(
	clk16x		=> clk,
	rxd			=> rxd,
	rgb_sel		=> rgb_sel,
	level1		=> level1,
	level2		=> level2,
	level3		=> level3,
	time1		=> time1,
	time2		=> time2,
	time3		=> time3,
	panel_sel	=> panel_sel,
	auto		=> auto,
	levellow	=> levellow,
	levelhigh	=> levelhigh,
	panel		=> panel,
	amp			=> amp
);

end;