image.map.rpt

FPGA的串口通信程序

    Info: Duplicate register "image1:U2|shinningblock:U2|out2_b_o[7]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[7]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_g_e[6]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[6]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_b_e[6]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[6]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_r_o[6]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[6]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_g_o[6]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[6]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_b_o[6]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[6]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_g_e[5]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[5]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_b_e[5]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[5]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_r_o[5]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[5]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_g_o[5]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[5]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_b_o[5]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[5]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_g_e[4]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[4]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_b_e[4]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[4]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_r_o[4]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[4]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_g_o[4]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[4]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_b_o[4]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[4]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_g_e[3]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[3]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_b_e[3]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[3]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_r_o[3]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[3]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_g_o[3]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[3]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_b_o[3]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[3]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_g_e[2]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[2]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_b_e[2]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[2]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_r_o[2]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[2]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_g_o[2]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[2]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_b_o[2]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[2]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_g_e[1]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[1]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_b_e[1]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[1]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_r_o[1]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[1]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_g_o[1]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[1]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_b_o[1]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[1]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_g_e[0]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[0]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_b_e[0]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[0]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_r_o[0]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[0]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_g_o[0]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[0]"
    Info: Duplicate register "image1:U2|shinningblock:U2|out2_b_o[0]" merged to single register "image1:U2|shinningblock:U2|out2_r_e[0]"
    Info: Duplicate register "image1:U2|out1_g_e[7]" merged to single register "image1:U2|out1_r_e[7]"
    Info: Duplicate register "image1:U2|out1_b_e[7]" merged to single register "image1:U2|out1_r_e[7]"
    Info: Duplicate register "image1:U2|out1_r_o[7]" merged to single register "image1:U2|out1_r_e[7]"
    Info: Duplicate register "image1:U2|out1_g_o[7]" merged to single register "image1:U2|out1_r_e[7]"
    Info: Duplicate register "image1:U2|out1_b_o[7]" merged to single register "image1:U2|out1_r_e[7]"
    Info: Duplicate register "image1:U2|out1_g_e[6]" merged to single register "image1:U2|out1_r_e[6]"
    Info: Duplicate register "image1:U2|out1_b_e[6]" merged to single register "image1:U2|out1_r_e[6]"
    Info: Duplicate register "image1:U2|out1_r_o[6]" merged to single register "image1:U2|out1_r_e[6]"
    Info: Duplicate register "image1:U2|out1_g_o[6]" merged to single register "image1:U2|out1_r_e[6]"
    Info: Duplicate register "image1:U2|out1_b_o[6]" merged to single register "image1:U2|out1_r_e[6]"
    Info: Duplicate register "image1:U2|out1_g_e[5]" merged to single register "image1:U2|out1_r_e[5]"
    Info: Duplicate register "image1:U2|out1_b_e[5]" merged to single register "image1:U2|out1_r_e[5]"
    Info: Duplicate register "image1:U2|out1_r_o[5]" merged to single register "image1:U2|out1_r_e[5]"
    Info: Duplicate register "image1:U2|out1_g_o[5]" merged to single register "image1:U2|out1_r_e[5]"
    Info: Duplicate register "image1:U2|out1_b_o[5]" merged to single register "image1:U2|out1_r_e[5]"
    Info: Duplicate register "image1:U2|out1_g_e[4]" merged to single register "image1:U2|out1_r_e[4]"
    Info: Duplicate register "image1:U2|out1_b_e[4]" merged to single register "image1:U2|out1_r_e[4]"
    Info: Duplicate register "image1:U2|out1_r_o[4]" merged to single register "image1:U2|out1_r_e[4]"
    Info: Duplicate register "image1:U2|out1_g_o[4]" merged to single register "image1:U2|out1_r_e[4]"
    Info: Duplicate register "image1:U2|out1_b_o[4]" merged to single register "image1:U2|out1_r_e[4]"
    Info: Duplicate register "image1:U2|out1_g_e[3]" merged to single register "image1:U2|out1_r_e[3]"
    Info: Duplicate register "image1:U2|out1_b_e[3]" merged to single register "image1:U2|out1_r_e[3]"
    Info: Duplicate register "image1:U2|out1_r_o[3]" merged to single register "image1:U2|out1_r_e[3]"
    Info: Duplicate register "image1:U2|out1_g_o[3]" merged to single register "image1:U2|out1_r_e[3]"
    Info: Duplicate register "image1:U2|out1_b_o[3]" merged to single register "image1:U2|out1_r_e[3]"
    Info: Duplicate register "image1:U2|out1_g_e[2]" merged to single register "image1:U2|out1_r_e[2]"
    Info: Duplicate register "image1:U2|out1_b_e[2]" merged to single register "image1:U2|out1_r_e[2]"
    Info: Duplicate register "image1:U2|out1_r_o[2]" merged to single register "image1:U2|out1_r_e[2]"
    Info: Duplicate register "image1:U2|out1_g_o[2]" merged to single register "image1:U2|out1_r_e[2]"
    Info: Duplicate register "image1:U2|out1_b_o[2]" merged to single register "image1:U2|out1_r_e[2]"
    Info: Duplicate register "image1:U2|out1_g_e[1]" merged to single register "image1:U2|out1_r_e[1]"
    Info: Duplicate register "image1:U2|out1_b_e[1]" merged to single register "image1:U2|out1_r_e[1]"
    Info: Duplicate register "image1:U2|out1_r_o[1]" merged to single register "image1:U2|out1_r_e[1]"
    Info: Duplicate register "image1:U2|out1_g_o[1]" merged to single register "image1:U2|out1_r_e[1]"
    Info: Duplicate register "image1:U2|out1_b_o[1]" merged to single register "image1:U2|out1_r_e[1]"
    Info: Duplicate register "image1:U2|out1_g_e[0]" merged to single register "image1:U2|out1_r_e[0]"
    Info: Duplicate register "image1:U2|out1_b_e[0]" merged to single register "image1:U2|out1_r_e[0]"
    Info: Duplicate register "image1:U2|out1_r_o[0]" merged to single register "image1:U2|out1_r_e[0]"
    Info: Duplicate register "image1:U2|out1_g_o[0]" merged to single register "image1:U2|out1_r_e[0]"
    Info: Duplicate register "image1:U2|out1_b_o[0]" merged to single register "image1:U2|out1_r_e[0]"
Warning: Reduced register "rs232_r:U1|rcv:u2|auto[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "rs232_r:U1|rcv:u2|auto[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "rs232_r:U1|rcv:u2|auto[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "rs232_r:U1|rcv:u2|auto[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "rs232_r:U1|rcv:u2|auto[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "rs232_r:U1|rcv:u2|auto[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "rs232_r:U1|rcv:u2|auto[0]" with stuck data_in port to stuck value GND
Info: Duplicate registers merged to single register
    Info: Duplicate register "image1:U2|out_r_o[7]" merged to single register "image1:U2|out_r_e[7]"
    Info: Duplicate register "image1:U2|out_r_o[6]" merged to single register "image1:U2|out_r_e[6]"
    Info: Duplicate register "image1:U2|out_r_o[5]" merged to single register "image1:U2|out_r_e[5]"
    Info: Duplicate register "image1:U2|out_r_o[4]" merged to single register "image1:U2|out_r_e[4]"
    Info: Duplicate register "image1:U2|out_r_o[3]" merged to single register "image1:U2|out_r_e[3]"
    Info: Duplicate register "image1:U2|out_r_o[2]" merged to single register "image1:U2|out_r_e[2]"
    Info: Duplicate register "image1:U2|out_r_o[1]" merged to single register "image1:U2|out_r_e[1]"
    Info: Duplicate register "image1:U2|out_r_o[0]" merged to single register "image1:U2|out_r_e[0]"
    Info: Duplicate register "image1:U2|out_b_o[7]" merged to single register "image1:U2|out_b_e[7]"
    Info: Duplicate register "image1:U2|out_b_o[6]" merged to single register "image1:U2|out_b_e[6]"
    Info: Duplicate register "image1:U2|out_b_o[5]" merged to single register "image1:U2|out_b_e[5]"
    Info: Duplicate register "image1:U2|out_b_o[4]" merged to single register "image1:U2|out_b_e[4]"
    Info: Duplicate register "image1:U2|out_b_o[3]" merged to single register "image1:U2|out_b_e[3]"
    Info: Duplicate register "image1:U2|out_b_o[2]" merged to single register "image1:U2|out_b_e[2]"
    Info: Duplicate register "image1:U2|out_b_o[1]" merged to single register "image1:U2|out_b_e[1]"
    Info: Duplicate register "image1:U2|out_b_o[0]" merged to single register "image1:U2|out_b_e[0]"
    Info: Duplicate register "image1:U2|out_g_o[7]" merged to single register "image1:U2|out_g_e[7]"
    Info: Duplicate register "image1:U2|out_g_o[6]" merged to single register "image1:U2|out_g_e[6]"
    Info: Duplicate register "image1:U2|out_g_o[5]" merged to single register "image1:U2|out_g_e[5]"
    Info: Duplicate register "image1:U2|out_g_o[4]" merged to single register "image1:U2|out_g_e[4]"
    Info: Duplicate register "image1:U2|out_g_o[3]" merged to single register "image1:U2|out_g_e[3]"
    Info: Duplicate register "image1:U2|out_g_o[2]" merged to single register "image1:U2|out_g_e[2]"
    Info: Duplicate register "image1:U2|out_g_o[1]" merged to single register "image1:U2|out_g_e[1]"
    Info: Duplicate register "image1:U2|out_g_o[0]" merged to single register "image1:U2|out_g_e[0]"
    Info: Duplicate register "rs232_r:U1|rcv:u2|panel[0]" merged to single register "rs232_r:U1|rcv:u2|panel[1]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "rs232_t:u5|pll1:u1|number[0]" merged to single register "rs232_r:U1|pll1:u1|number[0]"
Warning: Reduced register "rs232_r:U1|rcv:u2|panel[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "rs232_r:U1|rcv:u2|rgb_sel[1]" with stuck data_in port to stuck value GND
Info: Power-up level of register "rs232_r:U1|rcv:u2|rgb_sel[0]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "rs232_r:U1|rcv:u2|rgb_sel[0]" with stuck data_in port to stuck value VCC
Info: State machine "|image|image1:U2|shinningblock:U2|state" contains 4 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|image|image1:U2|shinningblock:U2|state"
Info: Encoding result for state machine "|image|image1:U2|shinningblock:U2|state"
    Info: Completed encoding using 4 state bits
        Info: Encoded state bit "image1:U2|shinningblock:U2|state.state3"
        Info: Encoded state bit "image1:U2|shinningblock:U2|state.state2"
        Info: Encoded state bit "image1:U2|shinningblock:U2|state.state1"
        Info: Encoded state bit "image1:U2|shinningblock:U2|state.tristate"
    Info: State "|image|image1:U2|shinningblock:U2|state.tristate" uses code string "0000"
    Info: State "|image|image1:U2|shinningblock:U2|state.state1" uses code string "0011"
    Info: State "|image|image1:U2|shinningblock:U2|state.state2" uses code string "0101"
    Info: State "|image|image1:U2|shinningblock:U2|state.state3" uses code string "1001"
Info: Duplicate registers merged to single register
    Info: Duplicate register "rs232_r:U1|pll1:u1|number[1]" merged to single register "rs232_t:u5|pll1:u1|number[1]"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "pixs_out" stuck at VCC
Warning: Output port clk0 of PLL "pll:U3|altpll:altpll_component|pll" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance.
Info: Implemented 1100 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 58 output pins
    Info: Implemented 1 bidirectional pins
    Info: Implemented 1039 logic cells
    Info: Implemented 1 ClockLock PLLs
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 27 warnings
    Info: Processing ended: Mon Apr 21 09:41:16 2008
    Info: Elapsed time: 00:00:18