image.vhd

FPGA的串口通信程序

LIBRARY ieee ;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
use ieee.std_logic_arith.all ;

ENTITY image IS								--总体框架，各个器件的物理连接
PORT(   rxd      : INOUT std_logic;
        clk      : IN std_logic;
		txd      : out std_logic;
        clk_out  : OUT std_logic;
		hs_out   : OUT std_logic;
		de_out   : BUFFER std_logic;
		vs_out   : OUT std_logic;
		pixs_out :OUT std_logic;
		trigger  : OUT std_logic;
		panelsel : out std_logic;
		pu		 : out std_logic;
		pd		 : out std_logic;
		out_r_e  : OUT std_logic_vector(7 DOWNTO 0);
		out_g_e  : OUT std_logic_vector(7 DOWNTO 0);
		out_b_e  : OUT std_logic_vector(7 DOWNTO 0);
		out_r_o  : OUT std_logic_vector(7 DOWNTO 0);
		out_g_o  : OUT std_logic_vector(7 DOWNTO 0);
		out_b_o  : OUT std_logic_vector(7 DOWNTO 0)
);
end image;

ARCHITECTURE rtl OF image IS
signal clk_in   : std_logic;
signal clkx     : std_logic;
signal datain   :  std_logic_vector(7  downto 0);
SIGNAL rgb_sel  :  std_logic_vector(7  DOWNTO 0);
SIGNAL level1   :  std_logic_vector(7  DOWNTO 0);
SIGNAl level2   :  std_logic_vector(7  DOWNTO 0);
SIGNAl level3   :  std_logic_vector(7  DOWNTO 0);
SIGNAl time1    :  std_logic_vector(7  DOWNTO 0);
SIGNAl time2    :  std_logic_vector(7  DOWNTO 0);
SIGNAl time3    :  std_logic_vector(7  DOWNTO 0);
SIGNAl panel_sel:  std_logic_vector(7  DOWNTO 0);
SIGNAL auto		:  std_logic_vector(7  DOWNTO 0);
SIGNAL levellow	:  std_logic_vector(7  DOWNTO 0);
SIGNAL levelhigh:  std_logic_vector(7  DOWNTO 0);
SIGNAl panel	:  std_logic_vector(7  DOWNTO 0);
SIGNAl amp1		:  std_logic_vector(7  DOWNTO 0);
signal countx	   :  unsigned (23 downto 0);

component image1
PORT(   clk     : IN std_logic;
		ctrl	: in std_logic;
		hs_out  : OUT std_logic;
		de_out  : BUFFER std_logic;
		vs_out  : OUT std_logic;
		pixs_out: OUT std_logic;
		trigger : OUT std_logic;
		datain  : out std_logic_vector(7 downto 0);
		rgb_sel : IN std_logic_vector (7 downto 0);
		level1  : IN std_logic_vector (7 downto 0);
		level2  : IN std_logic_vector (7 downto 0);
		level3  : IN std_logic_vector (7 downto 0);
		time1	: IN std_logic_vector (7 downto 0);
		time2	: IN std_logic_vector (7 downto 0);
		time3	: IN std_logic_vector (7 downto 0);
		panel_sel:IN std_logic_vector (7 downto 0);
	    auto	 :in std_logic_vector (7 downto 0);
	    levellow :in std_logic_vector (7 downto 0);	
	    levelhigh:in std_logic_vector (7 downto 0);	--自动测量
		out_r_e  :OUT std_logic_vector(7 DOWNTO 0);
		out_g_e  :OUT std_logic_vector(7 DOWNTO 0);
		out_b_e  :OUT std_logic_vector(7 DOWNTO 0);
		out_r_o  :OUT std_logic_vector(7 DOWNTO 0);
		out_g_o  :OUT std_logic_vector(7 DOWNTO 0);
		out_b_o  :OUT std_logic_vector(7 DOWNTO 0));
end component;


component pll
PORT
(
		inclk0	: IN STD_LOGIC  := '0';
		c0		: OUT STD_LOGIC 
);
end component;

component rs232_t is
port
(
	  clk  		: in  std_logic ;
   	  ctrl	: in  std_logic;
	  datain	: in  std_logic_vector (7 downto 0);
	  txd    	: out std_logic
);
end component;

COMPONENT rs232_r IS 
port (inclk, rxd: in std_logic ;
	  rgb_sel   : out std_logic_vector (7 downto 0);
	  level1    : out std_logic_vector (7 downto 0);
	  level2    : out std_logic_vector (7 downto 0);
	  level3    : out std_logic_vector (7 downto 0);
	  time1     : out std_logic_vector (7 downto 0);
	  time2     : out std_logic_vector (7 downto 0);
	  time3     : out std_logic_vector (7 downto 0);
	  panel_sel : out std_logic_vector (7 downto 0);
	  auto		: out std_logic_vector (7 downto 0);
	  levellow	: out std_logic_vector (7 downto 0);	
	  levelhigh : out std_logic_vector (7 downto 0);	--自动测量
	  panel     : out std_logic_vector (7 downto 0);
	  amp	    : out std_logic_vector (7 downto 0)
) ;
END COMPONENT;

COMPONENT amp IS 
port (clk	 	: in std_logic ;
   	  panel 	: in std_logic_vector (7 downto 0);
	  amp	  	: in std_logic_vector (7 downto 0);
	  panelsel 	: out std_logic;
	  pu  		: out std_logic;
	  pd   		: out std_logic
);
END COMPONENT;

begin
U3 : pll
PORT MAP
(
		inclk0	=>	clk, 
		c0		=>	clk_in
);
	
U4 : amp
PORT MAP
(
		clk		=>	clk, 
		panel	=>	panel,
		amp		=>  amp1,
		panelsel=>  panelsel,
		pu		=>  pu,
		pd		=>	pd
);

u5: rs232_t
port map
(
		clk		=>clk,
		ctrl	=>clkx,
		datain  => datain,
		txd		=>txd
);

U1: rs232_r
PORT MAP
(
		inclk	=>clk,
		rxd		=>rxd,
		rgb_sel	=>rgb_sel,
		level1	=>level1,
		level2	=>level2,
		level3	=>level3,
		time1	=>time1,
		time2	=>time2,
		time3	=>time3,
		panel_sel=>panel_sel,
		auto	 =>auto,
		levellow =>levellow,
		levelhigh=>levelhigh,
		panel	=>panel,
		amp		=>amp1
);

	
U2 :image1
PORT MAP
(
        clk      =>clk_in,
		ctrl	 =>clkx,
		hs_out   =>hs_out,
		de_out   =>de_out,
		vs_out   =>vs_out,
		pixs_out =>pixs_out,
		trigger  =>trigger,
		datain   =>datain,
		rgb_sel	 =>rgb_sel,
		level1	 =>level1,
		level2	 =>level2,
		level3	 =>level3,
		time1	 =>time1,
		time2	 =>time2,
		time3	 =>time3,
		panel_sel=>panel_sel,
		auto	 =>auto,
		levellow =>levellow,
		levelhigh=>levelhigh,
		out_r_e  =>out_r_e,
		out_g_e  =>out_g_e,
		out_b_e  =>out_b_e,
		out_r_o  =>out_r_o,
		out_g_o  =>out_g_o,
		out_b_o  =>out_b_o
);

process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if std_logic_vector(countx) = "111101110011000101000000"  then
	 countx <= "000000000000000000000000";
else countx <= countx + "000000000000000000000001";
end if;
end if;
end process;

process(clk_in)
begin
if clk_in'event and clk_in = '1' then
if countx(23) = '1' then
	 clkx <= '0';
else clkx <= '1';
end if;
end if;
end process;			--产生自动测量系统中的控制信号，与程序中的trigger信号具有相似的步调

clk_out <= clk_in;

end rtl;