image.tan.rpt

FPGA的串口通信程序

+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                       ;
+--------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                      ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+--------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; pll:U3|altpll:altpll_component|_clk0 ;                    ; PLL output ; 54.0 MHz         ; 0.000 ns      ; 0.000 ns     ; clk      ; 27                    ; 20                  ; -1.885 ns ;              ;
; clk                                  ;                    ; User Pin   ; 40.0 MHz         ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A       ;              ;
+--------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'pll:U3|altpll:altpll_component|_clk0'                                                                                                                                                                                                                                          ;
+-----------------------------------------+-----------------------------------------------------+------------------------------+-----------------------+------------+--------------------------------------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                         ; To                    ; From Clock ; To Clock                             ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------+-----------------------+------------+--------------------------------------+-----------------------------+---------------------------+-------------------------+
; -6.783 ns                               ; None                                                ; rs232_r:U1|rcv:u2|rgb_sel[2] ; image1:U2|out_g_e[0]  ; clk        ; pll:U3|altpll:altpll_component|_clk0 ; 0.890 ns                    ; -4.388 ns                 ; 2.395 ns                ;
; -6.783 ns                               ; None                                                ; rs232_r:U1|rcv:u2|rgb_sel[2] ; image1:U2|out_g_e[4]  ; clk        ; pll:U3|altpll:altpll_component|_clk0 ; 0.890 ns                    ; -4.388 ns                 ; 2.395 ns                ;
; -6.782 ns                               ; None                                                ; rs232_r:U1|rcv:u2|rgb_sel[2] ; image1:U2|out_g_e[5]  ; clk        ; pll:U3|altpll:altpll_component|_clk0 ; 0.890 ns                    ; -4.388 ns                 ; 2.394 ns                ;
; -6.780 ns                               ; None                                                ; rs232_r:U1|rcv:u2|rgb_sel[2] ; image1:U2|out_b_e[0]  ; clk        ; pll:U3|altpll:altpll_component|_clk0 ; 0.890 ns                    ; -4.388 ns                 ; 2.392 ns                ;
; -6.779 ns                               ; None                                                ; rs232_r:U1|rcv:u2|rgb_sel[2] ; image1:U2|out_g_e[1]  ; clk        ; pll:U3|altpll:altpll_component|_clk0 ; 0.890 ns                    ; -4.388 ns                 ; 2.391 ns                ;
; -6.779 ns                               ; None                                                ; rs232_r:U1|rcv:u2|rgb_sel[2] ; image1:U2|out_g_e[2]  ; clk        ; pll:U3|altpll:altpll_component|_clk0 ; 0.890 ns                    ; -4.388 ns                 ; 2.391 ns                ;
; -6.779 ns                               ; None                                                ; rs232_r:U1|rcv:u2|rgb_sel[2] ; image1:U2|out_g_e[7]  ; clk        ; pll:U3|altpll:altpll_component|_clk0 ; 0.890 ns                    ; -4.388 ns                 ; 2.391 ns                ;
; -6.779 ns                               ; None                                                ; rs232_r:U1|rcv:u2|rgb_sel[2] ; image1:U2|out_b_e[1]  ; clk        ; pll:U3|altpll:altpll_component|_clk0 ; 0.890 ns                    ; -4.388 ns                 ; 2.391 ns                ;
; -6.778 ns                               ; None                                                ; rs232_r:U1|rcv:u2|rgb_sel[2] ; image1:U2|out_b_e[7]  ; clk        ; pll:U3|altpll:altpll_component|_clk0 ; 0.890 ns                    ; -4.388 ns                 ; 2.390 ns                ;
; -6.777 ns                               ; None                                                ; rs232_r:U1|rcv:u2|rgb_sel[2] ; image1:U2|out_r_e[2]  ; clk        ; pll:U3|altpll:altpll_component|_clk0 ; 0.890 ns                    ; -4.388 ns                 ; 2.389 ns                ;
; -6.777 ns                               ; None                                                ; rs232_r:U1|rcv:u2|rgb_sel[2] ; image1:U2|out_g_e[6]  ; clk        ; pll:U3|altpll:altpll_component|_clk0 ; 0.890 ns                    ; -4.388 ns                 ; 2.389 ns                ;
; -6.776 ns                               ; None                                                ; rs232_r:U1|rcv:u2|rgb_sel[2] ; image1:U2|out_g_e[3]  ; clk        ; pll:U3|altpll:altpll_component|_clk0 ; 0.890 ns                    ; -4.388 ns                 ; 2.388 ns                ;
; -6.776 ns                               ; None                                                ; rs232_r:U1|rcv:u2|rgb_sel[2] ; image1:U2|out_b_e[4]  ; clk        ; pll:U3|altpll:altpll_component|_clk0 ; 0.890 ns                    ; -4.388 ns                 ; 2.388 ns                ;
; -6.774 ns                               ; None                                                ; rs232_r:U1|rcv:u2|rgb_sel[2] ; image1:U2|out_r_e[4]  ; clk        ; pll:U3|altpll:altpll_component|_clk0 ; 0.890 ns                    ; -4.388 ns                 ; 2.386 ns                ;
; -6.772 ns                               ; None                                                ; rs232_r:U1|rcv:u2|rgb_sel[2] ; image1:U2|out_b_e[2]  ; clk        ; pll:U3|altpll:altpll_component|_clk0 ; 0.890 ns                    ; -4.388 ns                 ; 2.384 ns                ;
; -6.771 ns                               ; None                                                ; rs232_r:U1|rcv:u2|rgb_sel[2] ; image1:U2|out_r_e[1]  ; clk        ; pll:U3|altpll:altpll_component|_clk0 ; 0.890 ns                    ; -4.388 ns                 ; 2.383 ns                ;
; -6.770 ns                               ; None                                                ; rs232_r:U1|rcv:u2|rgb_sel[2] ; image1:U2|out_r_e[7]  ; clk        ; pll:U3|altpll:altpll_component|_clk0 ; 0.890 ns                    ; -4.388 ns                 ; 2.382 ns                ;
; -6.769 ns                               ; None                                                ; rs232_r:U1|rcv:u2|rgb_sel[2] ; image1:U2|out_r_e[0]  ; clk        ; pll:U3|altpll:altpll_component|_clk0 ; 0.890 ns                    ; -4.388 ns                 ; 2.381 ns                ;