image.map.summary

FPGA的串口通信程序

Flow Status : Successful - Mon Apr 21 09:41:16 2008
Quartus II Version : 5.0 Build 168 06/22/2005 SP 1 SJ Full Version
Revision Name : image
Top-level Entity Name : image
Family : Cyclone
Device : EP1C6T144C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 1,039
Total pins : 60
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 1