4modelsim_work.mgf

altera i2c slave ip核verilog 编写

			(_register (sclr_viol))
		)
		(_tchk setuphold 0 712
			(_port clk (posedge) (_code  9 reset))
			(_port sload)
			(_register (sload_viol))
		)
		(_tchk setuphold 0 713
			(_port clk (posedge) (_code  10 reset))
			(_port ena)
			(_register (ena_viol))
		)
		(_modpath parallel positive 0 715
			(_port clk in posedge)
			(_port regout out posedge)
			(_datain iregout)
		)
		(_modpath parallel positive 0 716
			(_port aclr in posedge)
			(_port regout out posedge)
		)
		(_modpath parallel positive 0 717
			(_port aload in posedge)
			(_port regout out posedge)
			(_datain iregout)
		)
		(_modpath parallel unknown 0 718
			(_port datac in )
			(_port regout out )
		)
		(_modpath parallel positive 0 719
			(_port clk in posedge)
			(_port qfbkout out posedge)
			(_datain iregout)
		)
		(_modpath parallel positive 0 720
			(_port aclr in posedge)
			(_port qfbkout out posedge)
		)
		(_modpath parallel positive 0 721
			(_port aload in posedge)
			(_port qfbkout out posedge)
			(_datain iregout)
		)
		(_modpath parallel unknown 0 722
			(_port datac in )
			(_port qfbkout out )
		)
	)
)
V 000048 56 593 1071732054743 stratix_asynch_io
(_unit stratix_asynch_io
	(_specify
		(_modpath parallel unknown 0 890
			(_port padio in )
			(_port combout out )
		)
		(_modpath parallel unknown 0 891
			(_port datain in )
			(_port padio out )
		)
		(_modpath parallel positive 0 892
			(_port oe in posedge)
			(_port padio out posedge)
			(_datain padio_tmp)
		)
		(_modpath parallel positive 0 893
			(_port oe in negedge)
			(_port padio out negedge)
		)
		(_modpath parallel unknown 0 894
			(_port ddioregin in )
			(_port ddioregout out )
		)
		(_modpath parallel unknown 0 895
			(_port regin in )
			(_port regout out )
		)
	)
)
V 000050 56 785 1071732054752 stratix_io_register
(_unit stratix_io_register
	(_specify
		(_tchk setuphold 0 1060
			(_port clk (posedge) (_code  7 reset))
			(_port datain)
			(_register (datain_viol))
		)
		(_tchk setuphold 0 1061
			(_port clk (posedge) (_code  8 reset))
			(_port sreset)
			(_register (sreset_viol))
		)
		(_tchk setuphold 0 1062
			(_port clk (posedge) (_code  9 reset))
			(_port ena)
			(_register (ena_viol))
		)
		(_modpath parallel positive 0 1064
			(_port clk in posedge)
			(_port regout out posedge)
			(_datain iregout)
		)
		(_modpath parallel positive 0 1067
			(_code  10 is_areset_clear_EQ_1)
			(_port areset in posedge)
			(_port regout out posedge)
		)
		(_modpath parallel positive 0 1069
			(_code  11 is_areset_preset_EQ_1)
			(_port areset in posedge)
			(_port regout out posedge)
		)
	)
)
V 000052 56 1009 1071732054769 stratix_mac_register
(_unit stratix_mac_register
	(_specify
		(_specparam TCLR_MIN_PW integer 0)
		(_specparam TCLKL integer 0)
		(_specparam TPRE_MIN_PW integer 0)
		(_specparam TSU integer 0)
		(_specparam TCLKH integer 0)
		(_specparam TCLR integer 0)
		(_specparam TCO integer 0)
		(_specparam TCE_MIN_PW integer 0)
		(_specparam TCLK_MIN_PW integer 0)
		(_specparam TPRE integer 0)
		(_specparam TH integer 0)
		(_tchk setup 0 2392
			(_port data)
			(_port clk (posedge))
			(_register (viol_notifier))
		)
		(_tchk hold 0 2393
			(_port clk (posedge))
			(_port data)
			(_register (viol_notifier))
		)
		(_tchk setup 0 2394
			(_port ena)
			(_port clk (posedge))
			(_register (viol_notifier))
		)
		(_tchk hold 0 2395
			(_port clk (posedge))
			(_port ena)
			(_register (viol_notifier))
		)
		(_modpath parallel positive 0 2397
			(_port aclr in posedge)
			(_port dataout out posedge)
		)
		(_modpath parallel positive 0 2398
			(_port clk in posedge)
			(_port dataout out posedge)
			(_datain dataout_tmp)
		)
	)
)
V 000056 56 545 1071732054775 stratix_mac_mult_internal
(_unit stratix_mac_mult_internal
	(_specify
		(_modpath full unknown 0 1463
			(_port dataa in )
			(_port dataout out )
		)
		(_modpath full unknown 0 1464
			(_port datab in )
			(_port dataout out )
		)
		(_modpath parallel unknown 0 1465
			(_port dataa in )
			(_port scanouta out )
		)
		(_modpath parallel unknown 0 1466
			(_port datab in )
			(_port scanoutb out )
		)
		(_modpath full unknown 0 1467
			(_port signa in )
			(_port dataout out )
		)
		(_modpath full unknown 0 1468
			(_port signb in )
			(_port dataout out )
		)
	)
)
V 000056 56 1303 1071732054789 stratix_mac_out_internal
(_unit stratix_mac_out_internal
	(_specify
		(_modpath full unknown 0 1928
			(_port dataa in )
			(_port dataout out )
		)
		(_modpath full unknown 0 1929
			(_port datab in )
			(_port dataout out )
		)
		(_modpath full unknown 0 1930
			(_port datac in )
			(_port dataout out )
		)
		(_modpath full unknown 0 1931
			(_port datad in )
			(_port dataout out )
		)
		(_modpath full unknown 0 1932
			(_port signx in )
			(_port dataout out )
		)
		(_modpath full unknown 0 1933
			(_port signy in )
			(_port dataout out )
		)
		(_modpath full unknown 0 1934
			(_port addnsub0 in )
			(_port dataout out )
		)
		(_modpath full unknown 0 1935
			(_port addnsub1 in )
			(_port dataout out )
		)
		(_modpath full unknown 0 1936
			(_port zeroacc in )
			(_port dataout out )
		)
		(_modpath full unknown 0 1937
			(_port dataa in )
			(_port accoverflow out )
		)
		(_modpath full unknown 0 1938
			(_port signx in )
			(_port accoverflow out )
		)
		(_modpath full unknown 0 1939
			(_port signy in )
			(_port accoverflow out )
		)
		(_modpath full unknown 0 1940
			(_port addnsub0 in )
			(_port accoverflow out )
		)
		(_modpath full unknown 0 1941
			(_port addnsub1 in )
			(_port accoverflow out )
		)
		(_modpath full unknown 0 1942
			(_port zeroacc in )
			(_port accoverflow out )
		)
	)
)
V 000052 56 1322 1071732054795 stratix_ram_register
(_unit stratix_ram_register
	(_specify
		(_specparam TCLR_MIN_PW integer 0)
		(_specparam TCLKL integer 0)
		(_specparam TPRE_MIN_PW integer 0)
		(_specparam TSU integer 0)
		(_specparam TCLKH integer 0)
		(_specparam TCLR integer 0)
		(_specparam TCO integer 0)
		(_specparam TCE_MIN_PW integer 0)
		(_specparam TCLK_MIN_PW integer 0)
		(_specparam TPRE integer 0)
		(_specparam TH integer 0)
		(_tchk setup 0 2781
			(_port data)
			(_port clk (posedge))
			(_register (viol_notifier))
		)
		(_tchk setup 0 2782
			(_port aclr)
			(_port clk (posedge))
			(_register (viol_notifier))
		)
		(_tchk setup 0 2783
			(_port ena)
			(_port clk (posedge))
			(_register (viol_notifier))
		)
		(_tchk hold 0 2784
			(_port clk (posedge))
			(_port data)
			(_register (viol_notifier))
		)
		(_tchk hold 0 2785
			(_port clk (posedge))
			(_port aclr)
			(_register (viol_notifier))
		)
		(_tchk hold 0 2786
			(_port clk (posedge))
			(_port ena)
			(_register (viol_notifier))
		)
		(_modpath parallel positive 0 2788
			(_port aclr in posedge)
			(_port dataout out posedge)
		)
		(_modpath parallel positive 0 2789
			(_port clk in posedge)
			(_port dataout out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 2790
			(_port clk in posedge)
			(_port done out posedge)
			(_datain done_tbuf)
		)
	)
)
V 000051 56 952 1071732054805 stratix_ram_internal
(_unit stratix_ram_internal
	(_specify
		(_modpath full unknown 0 2992
			(_port port_a_write_enable in )
			(_port port_a_data_out out )
		)
		(_modpath full unknown 0 2993
			(_port port_b_write_enable in )
			(_port port_b_data_out out )
		)
		(_modpath full unknown 0 2994
			(_port port_a_data_in in )
			(_port port_a_data_out out )
		)
		(_modpath full unknown 0 2995
			(_port port_b_data_in in )
			(_port port_b_data_out out )
		)
		(_modpath full unknown 0 2996
			(_port port_a_address in )
			(_port port_a_data_out out )
		)
		(_modpath full unknown 0 2997
			(_port port_b_address in )
			(_port port_b_data_out out )
		)
		(_modpath full unknown 0 2998
			(_port port_a_byte_ena_mask in )
			(_port port_a_data_out out )
		)
		(_modpath full unknown 0 2999
			(_port port_b_byte_ena_mask in )
			(_port port_b_data_out out )
		)
		(_modpath full unknown 0 3000
			(_port port_b_read_enable in )
			(_port port_b_data_out out )
		)
	)
)
V 000065 56 2177 1071732054816 stratix_lvds_tx_parallel_register
(_unit stratix_lvds_tx_parallel_register
	(_specify
		(_modpath parallel positive 0 4588
			(_port clk in posedge)
			(_port dataout (_constant \0\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4589
			(_port clk in posedge)
			(_port dataout (_constant \1\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4590
			(_port clk in posedge)
			(_port dataout (_constant \2\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4591
			(_port clk in posedge)
			(_port dataout (_constant \3\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4592
			(_port clk in posedge)
			(_port dataout (_constant \4\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4593
			(_port clk in posedge)
			(_port dataout (_constant \5\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4594
			(_port clk in posedge)
			(_port dataout (_constant \6\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4595
			(_port clk in posedge)
			(_port dataout (_constant \7\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4596
			(_port clk in posedge)
			(_port dataout (_constant \8\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4597
			(_port clk in posedge)
			(_port dataout (_constant \9\) out posedge)
			(_datain dataout_tmp)
		)
		(_tchk setuphold 0 4599
			(_port clk (posedge))
			(_port datain)
		)
		(_tchk setuphold 0 4600
			(_port clk (posedge))
			(_port datain)
		)
		(_tchk setuphold 0 4601
			(_port clk (posedge))
			(_port datain)
		)
		(_tchk setuphold 0 4602
			(_port clk (posedge))
			(_port datain)
		)
		(_tchk setuphold 0 4603
			(_port clk (posedge))
			(_port datain)
		)
		(_tchk setuphold 0 4604
			(_port clk (posedge))
			(_port datain)
		)
		(_tchk setuphold 0 4605
			(_port clk (posedge))
			(_port datain)
		)
		(_tchk setuphold 0 4606
			(_port clk (posedge))
			(_port datain)
		)
		(_tchk setuphold 0 4607
			(_port clk (posedge))
			(_port datain)
		)
		(_tchk setuphold 0 4608
			(_port clk (posedge))
			(_port datain)
		)
	)
)
V 000056 56 341 1071732054821 stratix_lvds_tx_out_block
(_unit stratix_lvds_tx_out_block
	(_specify
		(_modpath parallel unknown 0 4693
			(_code  6 bypass_mode_EQ_1)
			(_port clk in )
			(_port dataout out )
		)
		(_modpath parallel positive 0 4696
			(_code  7 bypass_mode_EQ_0_AN_falling_clk_out_EQ_1)
			(_port clk in negedge)
			(_port dataout out negedge)
			(_datain dataout_tmp)
		)
	)
)
V 000065 56 1447 1071732054830 stratix_lvds_rx_parallel_register
(_unit stratix_lvds_rx_parallel_register
	(_specify
		(_modpath parallel positive 0 4927
			(_port clk in posedge)
			(_port dataout (_constant \0\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4928
			(_port clk in posedge)
			(_port dataout (_constant \1\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4929
			(_port clk in posedge)
			(_port dataout (_constant \2\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4930
			(_port clk in posedge)
			(_port dataout (_constant \3\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4931
			(_port clk in posedge)
			(_port dataout (_constant \4\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4932
			(_port clk in posedge)
			(_port dataout (_constant \5\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4933
			(_port clk in posedge)
			(_port dataout (_constant \6\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4934
			(_port clk in posedge)
			(_port dataout (_constant \7\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4935
			(_port clk in posedge)
			(_port dataout (_constant \8\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4936
			(_port clk in posedge)
			(_port dataout (_constant \9\) out posedge)
			(_datain dataout_tmp)
		)
	)
)
V 000041 56 35 1071732054862 stratix_pll
(_unit stratix_pll
	(_specify
	)
)