4modelsim_work.mgf

altera i2c slave ip核verilog 编写

		(_specparam TCO integer 0)
		(_specparam TCE_MIN_PW integer 0)
		(_specparam TCLK_MIN_PW integer 0)
		(_specparam TPRE integer 0)
		(_specparam TH integer 0)
		(_tchk setup 0 2781
			(_port data)
			(_port clk (posedge))
			(_register (viol_notifier))
		)
		(_tchk setup 0 2782
			(_port aclr)
			(_port clk (posedge))
			(_register (viol_notifier))
		)
		(_tchk setup 0 2783
			(_port ena)
			(_port clk (posedge))
			(_register (viol_notifier))
		)
		(_tchk hold 0 2784
			(_port clk (posedge))
			(_port data)
			(_register (viol_notifier))
		)
		(_tchk hold 0 2785
			(_port clk (posedge))
			(_port aclr)
			(_register (viol_notifier))
		)
		(_tchk hold 0 2786
			(_port clk (posedge))
			(_port ena)
			(_register (viol_notifier))
		)
		(_modpath parallel positive 0 2788
			(_port aclr in posedge)
			(_port dataout out posedge)
		)
		(_modpath parallel positive 0 2789
			(_port clk in posedge)
			(_port dataout out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 2790
			(_port clk in posedge)
			(_port done out posedge)
			(_datain done_tbuf)
		)
	)
)
I 000051 56 952 1071731857839 stratix_ram_internal
(_unit stratix_ram_internal
	(_specify
		(_modpath full unknown 0 2992
			(_port port_a_write_enable in )
			(_port port_a_data_out out )
		)
		(_modpath full unknown 0 2993
			(_port port_b_write_enable in )
			(_port port_b_data_out out )
		)
		(_modpath full unknown 0 2994
			(_port port_a_data_in in )
			(_port port_a_data_out out )
		)
		(_modpath full unknown 0 2995
			(_port port_b_data_in in )
			(_port port_b_data_out out )
		)
		(_modpath full unknown 0 2996
			(_port port_a_address in )
			(_port port_a_data_out out )
		)
		(_modpath full unknown 0 2997
			(_port port_b_address in )
			(_port port_b_data_out out )
		)
		(_modpath full unknown 0 2998
			(_port port_a_byte_ena_mask in )
			(_port port_a_data_out out )
		)
		(_modpath full unknown 0 2999
			(_port port_b_byte_ena_mask in )
			(_port port_b_data_out out )
		)
		(_modpath full unknown 0 3000
			(_port port_b_read_enable in )
			(_port port_b_data_out out )
		)
	)
)
I 000065 56 2177 1071731857848 stratix_lvds_tx_parallel_register
(_unit stratix_lvds_tx_parallel_register
	(_specify
		(_modpath parallel positive 0 4588
			(_port clk in posedge)
			(_port dataout (_constant \0\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4589
			(_port clk in posedge)
			(_port dataout (_constant \1\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4590
			(_port clk in posedge)
			(_port dataout (_constant \2\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4591
			(_port clk in posedge)
			(_port dataout (_constant \3\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4592
			(_port clk in posedge)
			(_port dataout (_constant \4\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4593
			(_port clk in posedge)
			(_port dataout (_constant \5\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4594
			(_port clk in posedge)
			(_port dataout (_constant \6\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4595
			(_port clk in posedge)
			(_port dataout (_constant \7\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4596
			(_port clk in posedge)
			(_port dataout (_constant \8\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4597
			(_port clk in posedge)
			(_port dataout (_constant \9\) out posedge)
			(_datain dataout_tmp)
		)
		(_tchk setuphold 0 4599
			(_port clk (posedge))
			(_port datain)
		)
		(_tchk setuphold 0 4600
			(_port clk (posedge))
			(_port datain)
		)
		(_tchk setuphold 0 4601
			(_port clk (posedge))
			(_port datain)
		)
		(_tchk setuphold 0 4602
			(_port clk (posedge))
			(_port datain)
		)
		(_tchk setuphold 0 4603
			(_port clk (posedge))
			(_port datain)
		)
		(_tchk setuphold 0 4604
			(_port clk (posedge))
			(_port datain)
		)
		(_tchk setuphold 0 4605
			(_port clk (posedge))
			(_port datain)
		)
		(_tchk setuphold 0 4606
			(_port clk (posedge))
			(_port datain)
		)
		(_tchk setuphold 0 4607
			(_port clk (posedge))
			(_port datain)
		)
		(_tchk setuphold 0 4608
			(_port clk (posedge))
			(_port datain)
		)
	)
)
I 000056 56 341 1071731857853 stratix_lvds_tx_out_block
(_unit stratix_lvds_tx_out_block
	(_specify
		(_modpath parallel unknown 0 4693
			(_code  6 bypass_mode_EQ_1)
			(_port clk in )
			(_port dataout out )
		)
		(_modpath parallel positive 0 4696
			(_code  7 bypass_mode_EQ_0_AN_falling_clk_out_EQ_1)
			(_port clk in negedge)
			(_port dataout out negedge)
			(_datain dataout_tmp)
		)
	)
)
I 000065 56 1447 1071731857862 stratix_lvds_rx_parallel_register
(_unit stratix_lvds_rx_parallel_register
	(_specify
		(_modpath parallel positive 0 4927
			(_port clk in posedge)
			(_port dataout (_constant \0\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4928
			(_port clk in posedge)
			(_port dataout (_constant \1\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4929
			(_port clk in posedge)
			(_port dataout (_constant \2\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4930
			(_port clk in posedge)
			(_port dataout (_constant \3\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4931
			(_port clk in posedge)
			(_port dataout (_constant \4\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4932
			(_port clk in posedge)
			(_port dataout (_constant \5\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4933
			(_port clk in posedge)
			(_port dataout (_constant \6\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4934
			(_port clk in posedge)
			(_port dataout (_constant \7\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4935
			(_port clk in posedge)
			(_port dataout (_constant \8\) out posedge)
			(_datain dataout_tmp)
		)
		(_modpath parallel positive 0 4936
			(_port clk in posedge)
			(_port dataout (_constant \9\) out posedge)
			(_datain dataout_tmp)
		)
	)
)
I 000041 56 35 1071731857887 stratix_pll
(_unit stratix_pll
	(_specify
	)
)
V 000035 56 942 1071732054669 dffe
(_unit dffe
	(_specify
		(_specparam TRSU integer 0)
		(_specparam TREN integer 0)
		(_specparam TREG integer 0)
		(_specparam TRCL integer 0)
		(_specparam TRH integer 0)
		(_specparam TRPR integer 0)
		(_tchk setup 0 132
			(_port D)
			(_port CLK (posedge) (_code  1 legal))
			(_register (viol_notifier))
		)
		(_tchk hold 0 133
			(_port CLK (posedge) (_code  2 legal))
			(_port D)
			(_register (viol_notifier))
		)
		(_tchk setup 0 134
			(_port ENA)
			(_port CLK (posedge) (_code  3 legal))
			(_register (viol_notifier))
		)
		(_tchk hold 0 135
			(_port CLK (posedge) (_code  4 legal))
			(_port ENA)
			(_register (viol_notifier))
		)
		(_modpath parallel positive 0 137
			(_port CLRN in negedge)
			(_port Q out negedge)
		)
		(_modpath parallel positive 0 138
			(_port PRN in negedge)
			(_port Q out negedge)
		)
		(_modpath parallel positive 0 139
			(_port CLK in posedge)
			(_port Q out posedge)
			(_datain D)
		)
	)
)
V 000036 56 558 1071732054676 latch
(_unit latch
	(_specify
		(_tchk setup 0 155
			(_port D)
			(_port ENA (posedge))
		)
		(_tchk hold 0 156
			(_port ENA (negedge))
			(_port D)
		)
		(_modpath parallel unknown 0 158
			(_port D in )
			(_port Q out )
		)
		(_modpath parallel positive 0 159
			(_port ENA in posedge)
			(_port Q out posedge)
			(_datain q_out)
		)
		(_modpath parallel positive 0 160
			(_port PRE in negedge)
			(_port Q out negedge)
			(_datain q_out)
		)
		(_modpath parallel positive 0 161
			(_port CLR in negedge)
			(_port Q out negedge)
			(_datain q_out)
		)
	)
)
V 000036 56 254 1071732054685 mux21
(_unit mux21
	(_specify
		(_modpath parallel unknown 0 210
			(_port A in )
			(_port MO out )
		)
		(_modpath parallel unknown 0 211
			(_port B in )
			(_port MO out )
		)
		(_modpath parallel unknown 0 212
			(_port S in )
			(_port MO out )
		)
	)
)
V 000035 56 104 1071732054695 and1
(_unit and1
	(_specify
		(_modpath parallel unknown 0 227
			(_port IN1 in )
			(_port Y out )
		)
	)
)
V 000036 56 105 1071732054700 and16
(_unit and16
	(_specify
		(_modpath parallel unknown 0 240
			(_port IN1 in )
			(_port Y out )
		)
	)
)
V 000052 56 2678 1071732054725 stratix_asynch_lcell
(_unit stratix_asynch_lcell
	(_specify
		(_modpath parallel unknown 0 352
			(_port dataa in )
			(_port combout out )
		)
		(_modpath parallel unknown 0 353
			(_port datab in )
			(_port combout out )
		)
		(_modpath parallel unknown 0 354
			(_port datac in )
			(_port combout out )
		)
		(_modpath parallel unknown 0 355
			(_port datad in )
			(_port combout out )
		)
		(_modpath parallel unknown 0 356
			(_port cin in )
			(_port combout out )
		)
		(_modpath parallel unknown 0 357
			(_port cin0 in )
			(_port combout out )
		)
		(_modpath parallel unknown 0 358
			(_port cin1 in )
			(_port combout out )
		)
		(_modpath parallel unknown 0 359
			(_port inverta in )
			(_port combout out )
		)
		(_modpath parallel unknown 0 360
			(_port qfbkin in )
			(_port combout out )
		)
		(_modpath parallel unknown 0 362
			(_port dataa in )
			(_port cout out )
		)
		(_modpath parallel unknown 0 363
			(_port datab in )
			(_port cout out )
		)
		(_modpath parallel unknown 0 364
			(_port cin in )
			(_port cout out )
		)
		(_modpath parallel unknown 0 365
			(_port cin0 in )
			(_port cout out )
		)
		(_modpath parallel unknown 0 366
			(_port cin1 in )
			(_port cout out )
		)
		(_modpath parallel unknown 0 367
			(_port inverta in )
			(_port cout out )
		)
		(_modpath parallel unknown 0 369
			(_port dataa in )
			(_port cout0 out )
		)
		(_modpath parallel unknown 0 370
			(_port datab in )
			(_port cout0 out )
		)
		(_modpath parallel unknown 0 371
			(_port cin0 in )
			(_port cout0 out )
		)
		(_modpath parallel unknown 0 372
			(_port inverta in )
			(_port cout0 out )
		)
		(_modpath parallel unknown 0 374
			(_port dataa in )
			(_port cout1 out )
		)
		(_modpath parallel unknown 0 375
			(_port datab in )
			(_port cout1 out )
		)
		(_modpath parallel unknown 0 376
			(_port cin1 in )
			(_port cout1 out )
		)
		(_modpath parallel unknown 0 377
			(_port inverta in )
			(_port cout1 out )
		)
		(_modpath parallel unknown 0 379
			(_port dataa in )
			(_port regin out )
		)
		(_modpath parallel unknown 0 380
			(_port datab in )
			(_port regin out )
		)
		(_modpath parallel unknown 0 381
			(_port datac in )
			(_port regin out )
		)
		(_modpath parallel unknown 0 382
			(_port datad in )
			(_port regin out )
		)
		(_modpath parallel unknown 0 383
			(_port cin in )
			(_port regin out )
		)
		(_modpath parallel unknown 0 384
			(_port cin0 in )
			(_port regin out )
		)
		(_modpath parallel unknown 0 385
			(_port cin1 in )
			(_port regin out )
		)
		(_modpath parallel unknown 0 386
			(_port inverta in )
			(_port regin out )
		)
		(_modpath parallel unknown 0 387
			(_port qfbkin in )
			(_port regin out )
		)
	)
)
V 000054 56 1583 1071732054730 stratix_lcell_register
(_unit stratix_lcell_register
	(_specify
		(_tchk setuphold 0 708
			(_port clk (posedge) (_code  5 reset))
			(_port regcascin)
			(_register (regcascin_viol))
		)
		(_tchk setuphold 0 709
			(_port clk (posedge) (_code  6 reset))
			(_port datain)
			(_register (datain_viol))
		)
		(_tchk setuphold 0 710
			(_port clk (posedge) (_code  7 reset))
			(_port datac)
			(_register (datac_viol))
		)
		(_tchk setuphold 0 711
			(_port clk (posedge) (_code  8 reset))
			(_port sclr)