led.vhd

在maxplusII上用VHDL语言编程实现的数字基带信号的同步提取

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY LED IS
PORT(
     CLK   :IN STD_LOGIC;
     Y     :OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END LED;
ARCHITECTURE A OF LED IS
SIGNAL Q:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN Y<=Q;
PROCESS(CLK)
BEGIN
IF(CLK'EVENT AND CLK='1')THEN
Q<=Q+'1';
END IF;
END PROCESS;
END A;