xs.vhd

在maxplusII上用VHDL语言编程实现的数字基带信号的同步提取

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY XS IS
PORT(
     D  :IN STD_LOGIC_VECTOR(3 DOWNTO 0);
     Y    :OUT STD_LOGIC_VECTOR(6 DOWNTO 0));
END XS;
ARCHITECTURE B OF XS IS
SIGNAL  E:STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN Y<=E;
PROCESS(D)
BEGIN
CASE D IS
WHEN"0000"=> E<="0111111";
WHEN"0001"=> E<="0000110";
WHEN"0010"=> E<="1011011";
WHEN"0011"=> E<="1001111";
WHEN"0100"=> E<="1100110";
WHEN"0101"=> E<="1101101";
WHEN"0110"=> E<="1111101";
WHEN"0111"=> E<="0000111";
WHEN"1000"=> E<="1111111";
WHEN"1001"=> E<="1101111";
WHEN"1010"=> E<="1110111";
WHEN"1011"=> E<="1111100";
WHEN"1100"=> E<="0111001";
WHEN"1101"=> E<="1011110";
WHEN"1110"=> E<="1111001";
WHEN"1111"=> E<="1110001";
WHEN OTHERS=>Y<="XXXXXXX";
END CASE;
END PROCESS;
END B;