cnt10.vhd

在maxplusII上用VHDL语言编程实现的数字基带信号的同步提取

library ieee;  
use ieee.std_logic_1164.all;  
use ieee.std_logic_unsigned.all;  
entity cnt10 is  
port(clk,ena,clr:in std_logic;  
 cq:out std_logic_vector(3 downto 0);  
 carry_out:out std_logic);  
end cnt10;  
architecture be_cnt10 of cnt10 is  
signal cq1:std_logic_vector(3 downto 0);  
begin  
process(clk,clr,ena)  
begin  
if clr='1' then  
 cq1<="0000";  
elsif clk'event and clk='1' then  
 if ena='1' then  
 if cq1="1001" then  
 cq1<="0000";  
 carry_out<='1';  
 else cq1<=cq1+1; 
 carry_out<='0';  
 end if;  
 end if;  
end if;  
end process;  
cq<=cq1;  
end be_cnt10;