📄 ztja.vhd
字号:
library IEEE;
use IEEE.std_logic_1164.all;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ztja is
port (
reset : in std_logic;
en : in std_logic;
keyin : in std_logic_vector (31 downto 0);
keyvalue : in std_logic_vector (3 downto 0);
keyout1 : out std_logic;
keyout2 : out std_logic;
keyout3 : out std_logic;
keyout4 : out std_logic;
z,clr : out std_logic );
end entity;
architecture ztja_arch of ztja is
type mystate is (s0,s1,s2,s3,s4);
signal m_state:mystate;
signal a: std_logic_vector (31 downto 0);
signal b: std_logic_vector (31 downto 0);
begin
process(en,m_state,reset)
begin
if reset='0' then
b<=X"00000001";
m_state<=s0;
elsif (en'event and en='1')then
a<=keyin;
case m_state is
when s0=>clr<='0';
if(keyvalue="1010") then
m_state<=s2;
else
m_state<=s0;
end if;
when s2=>if(b=keyin) then
clr<='1';
m_state<=s3;
else
clr<='1';
m_state<=s0;
end if;
when s3=>--if (keyvalue="1101") then
-- m_state<=s4;
--else m_state<=s0;
--end if;
--elsif(keyvalue="1110")then
--m_state<=s1;
--else m_state<=s0;
--end if;
case keyvalue is
when "1101"=>m_state<=s4;
when "1110"=>m_state<=s1;
when others=>m_state<=s0;
end case;
when s4=>if keyvalue="1111" then
m_state<=s0;
end if;
when s1=>clr<='0';
b<=keyin;
if keyvalue="1011" then
clr<='1';
m_state<=s0;
--end if;
end if;
end case;
end if;
end process;
keyout1<='1'when m_state=s0
else '0';
keyout2<='1'when m_state=s3
else '0';
keyout3<='1'when m_state=s4
else '0';
keyout4<='1'when m_state=s1
else '0';
z<='1'when m_state=s4
else '0';
end ztja_arch;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -