div256.vhd

来自「在maxplusII上用VHDL语言编程实现的数字基带信号的同步提取」· VHDL 代码 · 共 33 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY div256 IS
	PORT(clk             :IN  STD_LOGIC;
         div             :out std_logic);
         END div256;

ARCHITECTURE arc OF div256 IS
SIGNAL counter: std_logic_vector(7 downto 0);
BEGIN
div<=counter(7);
PROCESS(clk)
BEGIN
	IF(clk'event AND clk='1')THEN
      counter<=counter+1;
--if count<=
		--case counter is
       --when 0=>counter<=counter+1;
         -- div256<='1';
       --when 1 to 254  =>counter<=counter+1;
          --div256<='0';
       --when 255 =>counter<=0;
          --div256<='0';
       --when others=>counter<=0;
          --div256<='0';
    --end case;
   END IF;
END PROCESS;
END arc;