div2.vhd

在maxplusII上用VHDL语言编程实现的数字基带信号的同步提取

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY div2 IS
	PORT(clk             :IN  STD_LOGIC;
         div2             :out std_logic);
         END div2;

ARCHITECTURE arc OF div2 IS
SIGNAL counter: std_logic;
BEGIN
div2<=counter;
PROCESS(clk)
BEGIN
  	if clk'event and clk='1' then
 counter<=NOT counter;  
   END IF;
END PROCESS;
END arc;