mux8.vhd

在maxplusII上用VHDL语言编程实现的数字基带信号的同步提取

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

entity mux8 is
port(d:in std_logic_vector(31 downto 0);
     sel:in std_logic_vector(2 downto 0);
     y:out std_logic_vector(3 downto 0));
end mux8;

architecture rtl of mux8 is
signal s:std_logic_vector(2 downto 0);
signal n:std_logic_vector(3 downto 0);

begin
 s<=sel;
  process(d,sel)
  begin
    case s is
    when "111"=>n<=d(3 downto 0);
    when "110"=>n<=d(7 downto 4);
    when "101"=>n<=d(11 downto 8);
    when "100"=>n<=d(15 downto 12);
    when "011"=>n<=d(19 downto 16);
    when "010"=>n<=d(23 downto 20);
    when "001"=>n<=d(27 downto 24);
    when others=>n<=d(31 downto 28);
  end case;
  end process;
   y<=n;     
  end rtl;